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Why is noise margin in logic gates a quantitative measure of noise immunity? Can anyone provide an instantiation to demonstrate how noise margin is a measure of noise immunity enter image description here

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  • \$\begingroup\$ Your a programmer aren't you? \$\endgroup\$ – Andy aka Feb 19 '19 at 10:39
  • \$\begingroup\$ yes i program but also physics student \$\endgroup\$ – user212907 Feb 19 '19 at 21:23
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As you can see in the figures you attached with your question, for digital logic to work properly, the involved signals (usually voltages) have to follow the contract, that they need to be in the valid range described by the higher and lower voltage thresholds.
To allow for some noise in the system, the valid range for the inputs is a bit relaxed as compared to that for outputs. This allows for the margin for some noise without affecting the logical value of the result. For instance, if you pass the output of a digital block through a buffer, the interconnect noise or circuit noise could cause the output, expected to be below \$V_{OL}\$ to rise above this threshold. Consequently, the input threshold for the next stage,\$V_{IL}\$ is chosen higher than the \$V_{OL}\$. This ensures that noise in the range, \$NM_L=V_{IL}-V_{OL}\$ would not affect the logical result of the circuit. Thus, you have a noise margin of \$NM_L\$ in the lower threshold.
Similar argument can be made for the high threshold.

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