0
\$\begingroup\$

For a school assignment I have to make a counter, based on a 32-bit adder, that increments with 1 every clockcycle if 'enable = high' and 'reset = low'.

When I try to use the adder in my counter module, verilog gives me a syntax error which i dont know how to solve, near 'adder adder_count(.a(a), .b(b), .c(count));'

can anyone of you help?

 module half_adder(
    input a,
    input b,
    output sum,
    output Cout
    );

    assign sum = a ^ b;
    assign Cout = a & b;

endmodule

module full_adder(
    input Cin,
    input a,
    input b,
    output sum,
    output Cout
    );

    wire sum1_w;
    wire Cout1_w;
    wire Cout2_w;

    //Half adder 1

    half_adder half_add1 (.a(a), .b(b), .sum(sum1_w), .Cout(Cout1_w));

    //Half adder 2

    half_adder half_add2 (.a(Cin), .b(sum1_w), .sum(sum), .Cout(Cout2_w));   

    //Resulting OR gate

    or or_cout (Cout, Cout1_w, Cout2_w);

endmodule

module adder(
    input [31:0] a,
    input [31:0] b,
    output [31:0] c
    );

    wire [31:0] carry;
    genvar i;
    for (i = 0; i < 32; i = i + 1) begin
        if(i==0)
        half_adder half_add (.a(a[0]), .b(b[0]), .sum(c[0]), .Cout(carry[0]));

        else
        full_adder full_add (.Cin(carry[i-1]), .a(a[i]), .b(b[i]), .sum(c[i]), .Cout(carry[i]));

    end

endmodule 

module counter(
    input clk,
    input reset,
    input enable,
    output [3:0] count
    );

    reg [0:31] a;
    reg [0:31] b = 32'b00000000000000000000000000000001;
    // b starts as 1, a as 0

always @(posedge clk) begin

    if (enable == 1'b1 && reset == 1'b0) begin

        adder adder_count(.a(a), .b(b), .c(count));

        // every step:  a + 1 = c
        // a becomes c
        // repeat
    end 


     if (reset == 1'b1) begin
         //reset

     end
end

endmodule
\$\endgroup\$
6
  • 3
    \$\begingroup\$ When one is asking about syntax error, it is always a good idea to put the error text as is in the question. \$\endgroup\$
    – Eugene Sh.
    Feb 19 '19 at 17:39
  • 5
    \$\begingroup\$ You can't instantiate a module inside a procedural block. \$\endgroup\$
    – The Photon
    Feb 19 '19 at 17:41
  • 1
    \$\begingroup\$ A general advice: First draw a schematic of what you are trying to do. \$\endgroup\$
    – Eugene Sh.
    Feb 19 '19 at 17:43
  • \$\begingroup\$ @ThePhoton thanks! that seems to be the problem. However, now I need to figure out how to do it another way... \$\endgroup\$
    – e5m33
    Feb 19 '19 at 19:29
  • 1
    \$\begingroup\$ Put the adder outside the always block. Inside the always block, infer a flip-flop that captures the output of the adder when enable is asserted. You may need to create a new intermediate signal to be the output of the adder. \$\endgroup\$
    – The Photon
    Feb 19 '19 at 19:39
3
\$\begingroup\$

@ThePhoton gave the correct answer to your immediate problem, "You can't instantiate a module inside a procedural block."

But the whole approach is impractical for many other reasons. I understand why they make you build adders out of gates when you're learning the language, but continuing to use such techniques to build larger systems is just silly. You need to start using the power of the language to make your tasks easier. A counter in Verilog should be a 7-line block:

always @(posedge clock) begin
  if (reset) begin
    count <= 0;
  end else begin
    count <= count + 1;
  end
end

Which can be replaced by a single line if you want:

always @(posedge clock) count <= reset ? 0 : count + 1;

Keeping your source code simple makes it both easier to debug and easier to understand and extend later. It also gives you more room for comments that capture the design requirements and implementation constraints that are not visible in the code itself. THAT's the real lesson here!

\$\endgroup\$
2
  • \$\begingroup\$ Thanks for the help! I indeed know that there are easier ways to make a counter like you showed, but the assignment is very specific in using the 32-bit adder. I don't know why they want it like that... \$\endgroup\$
    – e5m33
    Feb 19 '19 at 19:28
  • \$\begingroup\$ @e5m33 FWIW, it is because your professor wants you to think in terms of "hardware", not "behavior". You are learning to design logic circuits, and, in this case, write structural HDL. Later on, when you are writing RTL at a higher-level, you will better understand how that count <= count + 1 will (likely) be implemented (target technology dependent to an extent). That, and while the design is probably the main topic, introducing you to an HDL at the same time is beneficial for you to learn to translate a circuit to HDL. This will pay off when you get that first job more easily. \$\endgroup\$
    – CapnJJ
    Feb 19 '19 at 20:17

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.