Is it possible to make a synthesizable hierarchy of constants in System Verilog?
- There is a board with FPGA and several peripheral ICs.
- Each IC have some setting registers.
- Each setting register has a number of parts.
- And each part has some possible values.
Is it possible to get these values with some like this DEV.REG.PART.VAL (not a DEV_REG_PART_VAL)?
Structs are not so excellent for making this hierarchy because of names intersection.
For example, there is a USB IC and a stepper-motor IC on board. A USB IC has a register SPEED with possible values LOW, HIGH and FULL. Stepper-motor IC also has a register SPEED with values 1RPM, 10RPM and 100RPM.
I would like to use a hierarchy like folders in a file system where I can create two different folders with the same names. And it is valid for all cases except "two identical names in one parent folder" (even same names parent and child folders).