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i wanted to ask what logic designs are used in industry for different logic functionalities?

So for example XOR gate: The 1st image would probably save more space on a circuit, but for the second design NAND gates are more convenient but require more space?

Are these assumptions correct, and are they any other propositions to be aware of? enter image description here

enter image description here

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    \$\begingroup\$ Such implementation detail can really only be discussed in terms of a given technology. If you are making an ASIC, you get the details from the vendor. If you are programming an FPGA, it's probably going to just end up in a LUT... And then there is the reality that signals may get inverted or re-calculated in multiple places if the tools determine that this is better than your conceptual design. We're far beyond the point where transistor level designs of logic is done manually, except in special cases, and you fail to state any specific motivations that make this a special case. \$\endgroup\$ Feb 19 '19 at 21:41
  • \$\begingroup\$ There is no difference in the CMOS counts between 1st and 2nd here. But transmission gates are commonly used. \$\endgroup\$ Feb 19 '19 at 21:42
  • \$\begingroup\$ I don't think any vendor would implement an XOR as shown in the first schematic, because B is either connected to the output through an inverter —with amplification— or straight-trough —without amplification. This makes it a mixed digital/analog element depending on logic states, which is not really marketable. \$\endgroup\$
    – Janka
    Feb 19 '19 at 21:58
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It is a mistake to focus only on gate count or transistor count to select the "best" implementation of a function. Modern synthesis tools are much more sophisticated.

We usually have timing constraints on a design, so the synthesizer may choose an implementation that requires more transistors and/or more silicon area just to make the circuit run fast enough.

Also, the intermediate results of some complex function might be useful. Suppose we needed to have \$\overline{AB}\$ as well as the exclusive OR. The third (pink?) implementation provides that for free, the others do not.

Circuits that are not fully restoring (i.e. pass signals through transmission gates) are usually not used as standard cells in digital design because it is so difficult to characterize their timing parameters as a function of output loading. Such circuits might be used inside custom macro cells, or in full-custom design at the transistor level.

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  • \$\begingroup\$ i.e. unless you plan on writing synthesis tools, or doing hand-layout physical design (backend), you won't ever have to "worry" about it in the "real world". Having said that, it is good that you think about it at this level, and, it is useful to understand the answers that were provided. In-practice though, It is unlikely that you will ever be gate-limited in most designs you work on. \$\endgroup\$
    – CapnJJ
    Feb 19 '19 at 22:20
  • \$\begingroup\$ Care to elaborate a bit on how more transistors can lead to things running faster? \$\endgroup\$
    – DKNguyen
    Feb 20 '19 at 2:38
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    \$\begingroup\$ @Toor Another option when driving heavy loads is simply to duplicate the logic driving the load and split the load between the two copies. Of course, these are techniques used in ASICs and full-custom VLSI. Your options are more limited in an FPGA. \$\endgroup\$ Feb 20 '19 at 13:07
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    \$\begingroup\$ @Toor A NAND gate has NMOS transistors in series, so the effective resistance pulling the output low is larger than that of an inverter, which has a single NMOS transistor. Likewise, NOR gates have PMOS transistors in series so they are slow to pull the output high. \$\endgroup\$ Feb 20 '19 at 15:22
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    \$\begingroup\$ @Toor A gate's propagation delays can be helped by making its transistors larger (increased W/L), which consumes more silicon area. In a sense this is equivalent to adding transistors in parallel. The manufacturing cost of an IC is actually determined by the silicon area rather than by the number of gates or transistors. \$\endgroup\$ Feb 20 '19 at 15:36

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