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As of RAM technologies (the basic ones) is concerned, I consider the initial classification (based on the storage) as

  • SRAM: The basic entity for storage (each cell) is the flip-flop (comprised of transistors). It does have a fast access compared to others.But it's expensive and space consuming due to the the number of transistors employed.

  • DRAM: Each cell is a transistor-capacitor circuit.The capacitor acts as a storage device, whereas transistor is the controlling unit which decides if a read/write should be performed on the specific cell. Also RAM controller needs to refresh the cells (meaning read and write back) at regular intervals to overcome the shortcoming of capacitor leakage

  • SDRAM: This is an succession of DRAM, except that the each operation on the RAM is synchronized with the system clock.

I am finding difficulties in understanding the advantage of making the RAM operations synchronous. Can anyone elaborate on this please ?

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The main advantage of synchronous design is that it's behavior is easy to predict, model, and validate because everything happens on a predefined schedule. However, waiting for a specified time to perform an action makes synchronous design slower than a comparable asynchronous design. And even when the circuit is not responding to its logic inputs, it is still drawing power since it is responding to the clock signal.

An asynchronous circuit can be much faster because it responds to its inputs as they change. No waiting around for a clock signal before processing can take place. They also can take less power since they don't have anything to do when the inputs are inactive and have better EMI performance since there isn't a constant digital signal floating around. But the design of such systems is much more difficult because all combinations of inputs over time need to be taken into consideration to ensure proper operation of the circuit. When two inputs change at almost the same time, this is called a race condition and the circuit can have undefined behavior if the designer didn't plan for every combination of inputs at every combination of time.

Comparing and contrasting synchronous to asynchronous design, you're probably thinking that big companies like Samsung can spend billions on the research and design to fully model a DRAM circuit so that its operation is really stable and then we would have really fast, really low power memory. So why is SDRAM so much more popular?

While asynchronous design is faster than synchronous in sequential operations, it is much much easier to design a circuit to perform parallel or simulations operations if the operations are synchronous. And when many operations can be performed at the same time, the speed advantage of asynchronous design disappears.

So three main things to consider when designing a RAM circuit are speed, power, and ease of design. SDRAM wins over plain DRAM on two out of three of those and by a very large margin.

Wikipedia quotes:

Dynamic random-access memory -

The most significant change, and the primary reason that SDRAM has supplanted asynchronous RAM, is the support for multiple internal banks inside the DRAM chip. Using a few bits of "bank address" which accompany each command, a second bank can be activated and begin reading data while a read from the first bank is in progress. By alternating banks, an SDRAM device can keep the data bus continuously busy, in a way that asynchronous DRAM cannot.

Synchronous dynamic random-access memory -

Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs. SDRAM has a synchronous interface, meaning that it waits for a clock signal before responding to control inputs and is therefore synchronized with the computer's system bus. The clock is used to drive an internal finite state machine that pipelines incoming commands. The data storage area is divided into several banks, allowing the chip to work on several memory access commands at a time, interleaved among the separate banks. This allows higher data access rates than an asynchronous DRAM.

Pipelining means that the chip can accept a new command before it has finished processing the previous one. In a pipelined write, the write command can be immediately followed by another command, without waiting for the data to be written to the memory array. In a pipelined read, the requested data appears after a fixed number of clock cycles after the read command (latency), clock cycles during which additional commands can be sent.

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  • \$\begingroup\$ But Dave Tweed says "Asynchronous DRAM is always slower...". Who is right? \$\endgroup\$ – Rocketmagnet Sep 28 '12 at 16:35
  • \$\begingroup\$ @Rocketmagnet If you took one bank of SDRAM and one bank of DRAM, the DRAM would be faster due to it's asynchronous nature because they both would have to perform sequentially. But SDRAM is never manufactured that way. SDRAM always made with several interleaved banks which allows for parallel operation. Because SDRAM is performing operations in parallel, it will always be faster than DRAM. \$\endgroup\$ – embedded.kyle Sep 28 '12 at 17:33
  • \$\begingroup\$ @Rocketmagnet Dave Tweed is 100% correct that DRAM is always slower than SDRAM. But the reason it's faster is because it uses interleaved banks. And the use of interleaved banks is made economically feasible due to it's synchronous nature. Figuring out the timing of interleaved banks of an asynchronous memory would be a nightmare. \$\endgroup\$ – embedded.kyle Sep 28 '12 at 17:35
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Asynchronous DRAM is always slower than synchronous DRAM in the same technology. This is because the RAS, CAS, WE and CS lines on DRAM need to be sequenced in a particular order to perform read and write operations on the chip. In addition to the minimum pulse widths on each of these lines, there are setup and hold times among various pairs of them that need to be allowed for, and together, all of these times add up to a relatively long cycle time.

By adding a common clock signal, an SDRAM eliminates all of those independent setup and hold time requirements; instead, all four lines have the same requirements relative to the common clock. This allows that clock to be much faster than the equivalent number of edges on the DRAM chip.

In addition, as the others have noted, the synchronous clock allows both the external interface and the internal operation of the SDRAM chip to be heavily pipelined, allowing many more individual reads and writes to occur in a given amount of time. The read latency might be a little more because of this pipelining, but the overall bandwidth of the memory is greatly improved.

I would note that there are also synchronous SRAMs (SSRAMs) that are used in high-performance systems for the same reasons.

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  • \$\begingroup\$ But embedded.kyle says "An asynchronous circuit can be much faster...". Who is right? \$\endgroup\$ – Rocketmagnet Sep 28 '12 at 16:35
  • \$\begingroup\$ Perhaps he means that in a more general sense, asynchronous logic has lower latencies than synchronous logic. But I have never seen a DRAM that was faster than an SDRAM implemented in the same generation of technology. In modern systems, throughput (bandwidth) is generally more important than latency anyway. Nobody puts the effort into DRAM design any more, since the SDRAM interface has become reasonably well standardized and it has all of those other advantages. \$\endgroup\$ – Dave Tweed Sep 28 '12 at 16:45
  • \$\begingroup\$ Have you worked with 1980s DRAM at all? I find it curious that repeated reads within a row aren't hugely faster than reads of different rows, and was wondering if bus driving was part of that? Since many NMOS devices are faster driving low than high, I wonder if speed could have been improved by precharging the bus lines between bytes? \$\endgroup\$ – supercat Jun 2 '16 at 17:45
  • \$\begingroup\$ @supercat: Yes, I have worked extensively with "old-fashioned" asynchronous DRAM. (I used to design motherboards for engineering workstations.) And yes, there were several varieties of chips that did take advantage of the fast access to data in a single row. For example, there was "nibble mode" (four adjacent bits in sequence), "fast page mode" (random access to any bit in the row) as well as special video RAMs (entire row transferred to a shift register and clocked out). But no, the physical bus interface had little to do with performance. \$\endgroup\$ – Dave Tweed Jun 2 '16 at 18:32
  • \$\begingroup\$ @DaveTweed: Do you have any idea why, internally, the time from /CAS to valid output was such a large fraction of total cycle time? I would think sense-amp stabilization would be a dominant factor. Many 1980s computers could have been much nicer if they could squeeze two consecutive-address video cycles along with one random-access CPU cycle into every eight dot clocks (rather than one video and one CPU) and if /CAS-to-output were a little faster that would be workable. \$\endgroup\$ – supercat Jun 3 '16 at 13:17
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In addition to Dave Tweed's answer, SDRAM clock is easier to layout. Specifically only the clock needs to be "clean". The other control pins can have glitches as long as 1) they don't violate over/undershoot requirements 2) they settle in time to meet SDRAM requirements.

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The memory array inside of a DRAM and SDRAM are essentially the same (although there are differences). The key to SDRAM is that it queues up the memory access so that you don't incur the same overhead for every access. So either in burst mode or in pipelining the access is not started and then stopped for every read/write. Internally the memory arrays are split into banks so activity can be occurring on one bank whilst other activity is finishing off in yet another. This means you have higher effective throughput all other factors being the same.

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  • \$\begingroup\$ As a side comment, the synchronous aspect allows you to design an interface that is DDR (double data rate) so for a given clock rate you can stuff 2X the amount of data up/down. An SDRAM is a collection of several different techniques that are used together to get higher access and throughput. \$\endgroup\$ – placeholder Sep 28 '12 at 15:19
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    \$\begingroup\$ It's worth noting that the internal memory array of a DRAM or SDRAM chip has a truly humongous bandwidth--being able to read out many thousands of bits on every access cycle; since chips don't have thousands of pins, only a small portion (probably less than 1%) of this bandwidth is normally exploited. Improving the memory interface design may thus enormously improve the bandwidth that can be achieved with a given memory array design. \$\endgroup\$ – supercat Sep 28 '12 at 15:52
  • \$\begingroup\$ @supercat excellent point! The memory array will be 1000's of column wide inside the chip. \$\endgroup\$ – placeholder Sep 28 '12 at 16:14
  • \$\begingroup\$ Many thousands of columns. Chips 64kbits and smaller would normally have been square grids (e.g. 64kbits would be 256x256); the number of rows, however, has not continued to increase as fast as the number of columns (since increasing the number of rows would increase the percentage of time one would have to spend on refresh). Thus, I don't think a quarter-gigabit chip would be a 16,384x16,384 grid; I would guess it would be more likely something like 1,024x262,144. Even if the grid was square, though, and even if the chip could only perform 10 million row accesses per second (pretty slow)... \$\endgroup\$ – supercat Sep 28 '12 at 17:24
  • \$\begingroup\$ ...that would represent a memory bandwidth of 160+ gigabits per second per memory chip. And that's with some very conservative assumptions. It's pretty clear there's a lot of potential memory bandwidth that unfortunately can't really be used; I would think putting a cache on the same chip as the DRAM array could boost system performance, but I don't know by how much. \$\endgroup\$ – supercat Sep 28 '12 at 17:27

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