SDRAM advantages

Question

As of RAM technologies (the basic ones) is concerned, I consider the initial classification (based on the storage) as

• SRAM: The basic entity for storage (each cell) is the flip-flop (comprised of transistors). It does have a fast access compared to others.But it's expensive and space consuming due to the the number of transistors employed.

• DRAM: Each cell is a transistor-capacitor circuit.The capacitor acts as a storage device, whereas transistor is the controlling unit which decides if a read/write should be performed on the specific cell. Also RAM controller needs to refresh the cells (meaning read and write back) at regular intervals to overcome the shortcoming of capacitor leakage

• SDRAM: This is an succession of DRAM, except that the each operation on the RAM is synchronized with the system clock.

I am finding difficulties in understanding the advantage of making the RAM operations synchronous. Can anyone elaborate on this please ?

Answer 1

The main advantage of synchronous design is that it's behavior is easy to predict, model, and validate because everything happens on a predefined schedule. However, waiting for a specified time to perform an action makes synchronous design slower than a comparable asynchronous design. And even when the circuit is not responding to its logic inputs, it is still drawing power since it is responding to the clock signal.

An asynchronous circuit can be much faster because it responds to its inputs as they change. No waiting around for a clock signal before processing can take place. They also can take less power since they don't have anything to do when the inputs are inactive and have better EMI performance since there isn't a constant digital signal floating around. But the design of such systems is much more difficult because all combinations of inputs over time need to be taken into consideration to ensure proper operation of the circuit. When two inputs change at almost the same time, this is called a race condition and the circuit can have undefined behavior if the designer didn't plan for every combination of inputs at every combination of time.

Comparing and contrasting synchronous to asynchronous design, you're probably thinking that big companies like Samsung can spend billions on the research and design to fully model a DRAM circuit so that its operation is really stable and then we would have really fast, really low power memory. So why is SDRAM so much more popular?

While asynchronous design is faster than synchronous in sequential operations, it is much much easier to design a circuit to perform parallel or simulations operations if the operations are synchronous. And when many operations can be performed at the same time, the speed advantage of asynchronous design disappears.

So three main things to consider when designing a RAM circuit are speed, power, and ease of design. SDRAM wins over plain DRAM on two out of three of those and by a very large margin.

Wikipedia quotes:

Dynamic random-access memory -

The most significant change, and the primary reason that SDRAM has supplanted asynchronous RAM, is the support for multiple internal banks inside the DRAM chip. Using a few bits of "bank address" which accompany each command, a second bank can be activated and begin reading data while a read from the first bank is in progress. By alternating banks, an SDRAM device can keep the data bus continuously busy, in a way that asynchronous DRAM cannot.

Synchronous dynamic random-access memory -

Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs. SDRAM has a synchronous interface, meaning that it waits for a clock signal before responding to control inputs and is therefore synchronized with the computer's system bus. The clock is used to drive an internal finite state machine that pipelines incoming commands. The data storage area is divided into several banks, allowing the chip to work on several memory access commands at a time, interleaved among the separate banks. This allows higher data access rates than an asynchronous DRAM.

Pipelining means that the chip can accept a new command before it has finished processing the previous one. In a pipelined write, the write command can be immediately followed by another command, without waiting for the data to be written to the memory array. In a pipelined read, the requested data appears after a fixed number of clock cycles after the read command (latency), clock cycles during which additional commands can be sent.

Answer 2

Asynchronous DRAM is always slower than synchronous DRAM in the same technology. This is because the RAS, CAS, WE and CS lines on DRAM need to be sequenced in a particular order to perform read and write operations on the chip. In addition to the minimum pulse widths on each of these lines, there are setup and hold times among various pairs of them that need to be allowed for, and together, all of these times add up to a relatively long cycle time.

By adding a common clock signal, an SDRAM eliminates all of those independent setup and hold time requirements; instead, all four lines have the same requirements relative to the common clock. This allows that clock to be much faster than the equivalent number of edges on the DRAM chip.

In addition, as the others have noted, the synchronous clock allows both the external interface and the internal operation of the SDRAM chip to be heavily pipelined, allowing many more individual reads and writes to occur in a given amount of time. The read latency might be a little more because of this pipelining, but the overall bandwidth of the memory is greatly improved.

I would note that there are also synchronous SRAMs (SSRAMs) that are used in high-performance systems for the same reasons.

Answer 3

In addition to Dave Tweed's answer, SDRAM clock is easier to layout. Specifically only the clock needs to be "clean". The other control pins can have glitches as long as 1) they don't violate over/undershoot requirements 2) they settle in time to meet SDRAM requirements.

Answer 4

The memory array inside of a DRAM and SDRAM are essentially the same (although there are differences). The key to SDRAM is that it queues up the memory access so that you don't incur the same overhead for every access. So either in burst mode or in pipelining the access is not started and then stopped for every read/write. Internally the memory arrays are split into banks so activity can be occurring on one bank whilst other activity is finishing off in yet another. This means you have higher effective throughput all other factors being the same.