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I have not used any BGA packages before, but (lucky for me) my first one is a 0.5mm pitch device.

Since the pitch is so fine, there is no room for vias between the pads, even at the smallest drill size of 0.2mm. For this reason, I have placed the decoupling capacitors on the same side as the BGA, rather than on the opposite side, as is usually recommended. The board thickness is 0.8mm. The passives are all 0201 packages.

I would be grateful if someone experienced with fine pitch BGAs could take a look and see if I have made any obvious mistakes. I have tried to clearly label all of the tracks with their functions, but please let me know if I can annotate the images better.

Top two layers Coloured tracks are on the top layer. The grey background is the ground plane on layer 2. BGA fanout 0.4mm pitch

Bottom two layers The coloured polygons are power planes on layer 4. The yellow track is on layer 3. BGA fanout 0.4mm pitch

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    \$\begingroup\$ Your BGA pads look quite small. Is this size within the recommendations of the chip manufacturer? \$\endgroup\$ – 1N4007 Feb 20 at 17:19
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    \$\begingroup\$ For one, keep the reference plane continuous to within three trace widths of the high speed traces on both sides. Something like 99% of the return current can be found within 3 trace widths. If you have a via too close, you’ll get a larger loop area as the current goes around. Also the same rule applies for the edges of reference planes. This is especially true for clocks. Furthermore try to avoid reference plane changes for the 12 MHz clock. The return current will go through the closest capacitor increasing the loop area. My 2c from a quick look. \$\endgroup\$ – user110971 Feb 20 at 17:42
  • \$\begingroup\$ What's the board material? In a multilayer design you should be able to get layer thicknesses down to at least 0.1 mm, allowing laser-drilled vias down to ~0.1 mm. At extra cost, of course, so if your 2-layer design works, stick with it. \$\endgroup\$ – The Photon Feb 20 at 20:00
  • \$\begingroup\$ @user110971 - Thanks. OK, I'll move that DVDD via away from the MIPI lines. I was trying to sandwich the 12MHz clock between two reference planes, but maybe I should just keep it on the top layer? \$\endgroup\$ – Rocketmagnet Feb 20 at 22:25
  • \$\begingroup\$ @Rocketmagnet Yes, keep the clock on the same layer. It needs to be monotonous. Even a small reflection or cross-talk can cause it to be non-monotonous. This can lead to timing violations that are intermittent and really difficult to debug. \$\endgroup\$ – user110971 Feb 20 at 22:28
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As already mentioned by 1N4007 the pads look rather small, verify the recommendations of the manufacturer, and if not specified, use IPC rules. Can you give details on the spacing and track width as well, the tracks look rather skinny as well.

Check the layout recommendations for the ground on pin D1. The track seems to be quite long, and might affect the performance of the MIPI lines.

Apart from the details mentioned above, the fanout is reasonable, and you seem to have followed good layout practices.

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  • \$\begingroup\$ My pads are 0.25mm. According to this Xilinx document (page 43), the pads should be 0.27mm. So they're pretty close. \$\endgroup\$ – Rocketmagnet Feb 20 at 22:29
  • \$\begingroup\$ Yes, that document is pretty good. 0.25mm should be fine. \$\endgroup\$ – Elmesito Feb 21 at 9:31

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