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This amplifier suits my purpose with one matter that I couldn’t figure out. Its output impedance is given as 0.01 Ohm. The output of this amplifier will be coupled to a very high input impedance(more than 20Meg) and balanced DAQ input via a balanced STP cable.

So the receiver is balanced, cable is balanced but not the amplifier output. Signal interest range can vary between 100mV to 5V and freq from DC up to 30kHz.

I want to obtain an impedance balanced output from this amplifier. What could be done right at the output of this amplifier to convert it to a impedance balanced output?

I thought about adding resistors to signal and reference leads but resistors have tolerances. How about cascading the output with this line driver?

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  • \$\begingroup\$ Are we missing the frequency range of interest and the amplitude of the signal? \$\endgroup\$ – Transistor Feb 20 '19 at 19:06
  • \$\begingroup\$ Range vary between 100mV to 5V and freq up to 30kHz. \$\endgroup\$ – user1999 Feb 20 '19 at 19:12
  • \$\begingroup\$ That needs to be specified in the question rather than tucked away in the comments. Hit the edit link below your question ... \$\endgroup\$ – Transistor Feb 20 '19 at 19:14
  • \$\begingroup\$ Alright doing it right away. \$\endgroup\$ – user1999 Feb 20 '19 at 19:15
  • \$\begingroup\$ How long is the interconnect cable and how much CM noise from power supply and what is insulation impedance relative to stray noise impedance? \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Feb 20 '19 at 21:16
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Get 2 ICs. Let one of them make 10(A-B) and let the other make 10(B-A), where A and B are the halves of the balanced input. You have the balanced output between the outputs of those two amps. Voltage gain = 20.

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  • \$\begingroup\$ You mean two INA106 by two ICs? Can we be sure the two ICs will have same output impedances? How about effect of temperature? Their output resistances will drift differently imao. But I dont have experince just pointed out my concern. \$\endgroup\$ – user1999 Feb 20 '19 at 19:10
  • \$\begingroup\$ Output impedances are very low due the feedback as long as you do not overload them, you can add series resistors, if needed. I can imagine 2 reasons to add them. 1) stability with long cables 2) protection against occasional accidental overvoltages. 20 MOhm load isn't a reason. Your own idea to use a dedicated unbalanced to balanced converter IC is surely ok, if its promised precision is ok for your purposes. \$\endgroup\$ – user287001 Feb 20 '19 at 19:26
  • \$\begingroup\$ That's wont reject stray noise on floating 0V \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Feb 20 '19 at 21:17
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I want to obtain an impedance balanced output

**I believe you mean your Diff Mode (DM) noise is poor and you think it is due to Diff Mode impedance balancing, when it is more likely CM impedance balance problems.

Possible sources of stray coupling unbalanced supply & cable impedance relative to ground.

schematic

simulate this circuit – Schematic created using CircuitLab

  • This DM mode balanced Z is not a problem for LF signals. ( e.g. 10 mOhm Audio Amp to 8 ohm HiFi is never a problem, actually it gives better Damping Factor.)
  • CM noise may be conducted by ground shift or radiating crosstalk but your cables and nearby E fields are the reasons for CM noise becoming DM noise.
  • PSU SMPS leakage capacitance of switching noise and stray grid voltage E-fields are the 2 most common issues for Common Mode (CM) noise getting converted to differential mode (DM) noise because of unbalanced CM impedance, not DM impedance.

This INA has high CMRR 86dB min 100dB typ.

  • 100 dB means the matching is 5 decades or 10 ppm.
    • A CMR of 106dB requires a resistor matching of 0.005%
  • The output impedance is near 0 because of open loop gain feedback, Aol Rout/Aol
  • the BW of this IC has a rise time much slower than expected prop delay of a cable
  • if \$t_r >> t_PD\$ then impedance matching of the signal has no effect since reflections are too slow, but it may affect RF stray noise where with short wavelengths

    • reduce RF ingress by using a ferrite CM choke or SMD Pi filter.

    • even if the rise time was near the cable prop delay using an R network, you would unlikely achieve this CMR with resistor arrays as these are internally laser-trimmed.

  • Your \$Z_{in} = R+ X_L+X_C\$ = 20Meg + ~10nH//cm + ~100 pF/m if there is connecting cable

  • the tolerance on L and C is uch higher than 10 ppm and is high depending on cable construction and not even close to INA specs
    • this can be improved significantly with shielded twisted pair (STP cable) with Gnd terminated at receiving end only. This must raise CM impedance so the differences are much less. ( by orders of magnitude ) Your source is near 0 so this is good, but the cable reactance is not so well matched with respect to your 0V ref ground.

Conclusions

The purpose of using INA IC's is for high CMRR so all other sources of CM degradation must be understood and taken care of. High levels of grid E-Field may not be rejected as well, so for low level signals, cables selection is critical and discrete Resistors should be avoided and CM noise of PSU is crucial often reduced by low leakage line filter to AC gnd or better methods of isolation than magnetic (capacitive coupling ) of windings.

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