I can think of a few ways to do this:
Use a demultiplexer with, say, the last 3 bits of the address bus as inputs, and then connect each output to the enable pin of a
different PIO chip. The issue I see here is, how do I then use the A/B
and C/D pins on the PIOs?
Use the first two bits of the address bus for A/B and C/D pins, and use the rest to indivually select each PIO chip. The issue here is
that unless I'm careful whilst addressing the ports, I could enable
two PIOs at the same time.
So long as you connect different address lines to A/B and C/D and each of the MUX address inputs it will be fine, even if the order is completely random. However some schemes can make programming easier and code more efficient.
Using A0 for C/D has the advantage of being able to switch between a PIO's control and data registers by adding or subtracting 1 from the I/O address, perhaps using INC C and DEC C or OUTI and OUTD instructions. This may save some instructions, making the code faster and more compact.
Using higher address lines for MUX addresses makes each PIO use a contiguous block of I/O addresses, vs being split between many address ranges. This doesn't affect operation in any way, but makes the I/O address map less confusing for designers and programmers.
If the I/O addresses are not 'fully decoded' then each PIO can be accessed at multiple 'mirror' addresses, but software only needs to know about the 'official' addresses.
Some commercial computer designs did not use a decoder at all, but simply connected a different address line to the /CE input each I/O device. If that address line was low then the device would be selected, but having more than one address line low at the same time would cause a bus contention and therefore was illegal. so the 'official' I/O map might look something like this:-
PIO 1 = 0x7F (A7 low)
PIO 2 = 0xBF (A6 low)
PIO 3 = 0xDF (A5 low)
This might seem dangerous because a software bug or glitch could cause multiple PIOs to be selected for reading at the same time, thus causing them to 'fight' for the data bus. However so long as only NMOS chips are used this is relatively safe, because the data bus drivers only pull low so they won't draw excessive current.