How to wire up multiple Z80 PIO chips?

Question

From my last question, I now understand how to use one Z80 PIO chip.

I'm having trouble understanding how I would wire multiple PIOs up, though. The more I think about it, the less sense it makes.

I mean, I can think of a few ways to do this:

• Use a demultiplexer with, say, the last 3 bits of the address bus as inputs, and then connect each output to the enable pin of a different PIO chip. The issue I see here is, how do I then use the A/B and C/D pins on the PIOs?
• Use the first two bits of the address bus for A/B and C/D pins, and use the rest to indivually select each PIO chip. The issue here is that unless I'm careful whilst addressing the ports, I could enable two PIOs at the same time.

So, none of these two ways seem to be the "right" way to do it. Is there a standard way of achieving multiple PIOs being controlled by the Z80?

Answer 1

I've never built a Z80 computer (or any other) but have had to explain basic micro-computer operation to maintenance personnel and I found this schematic very useful. With a little study you should be able to find a variety of clever techniques and tricks the designer used to get the most out of the limited number of address lines available.

Figure 1. The Z80 computer. (Click to enlarge.) Source: Z80.info.

The linked article and schematic are worth a read.

Is there a standard way of achieving multiple PIOs being controlled by the Z80?

Again, I have no expertise in this area but I imagine that every trick possible was used to get the best out of these devices.

Answer 2

Read carefully the Zilog Data book, it explains a lot. But some basic architectural features of common bus design are omitted there as obvious for a seasoned designer.

For novice it is important to understand the concept of address decoding and address mapping. In this particular case the I/O port chip occupies 4 consecutive addresses in I/O address space. Each internal register is selected by a combination on [A1:A0] address lines. But you have to design in the base address for this "cluster", which is usually done by selectively activating "CE" - chip enable input pin. Without this address selector any I/O access will go to one of four I/O port addreses.

To separate several I/O ports you need to design BASE ADDRESS DECODER using all upper address bits [Ax:A2] (whatever the address bus width is). The decoder must activate the individual CE signals ONLY WHEN the CPU code sends out this particular base address, and the rest of internal ports will be automatically selected by last two bits in the address. You need to design the address map by yourself and determine which areas of I/O space are free (available) and put the decoder there.

All other signals on the bus as RD/WR are common for all peripherals attached, but they have no effect unless the CE is active. The address decoder makes only one of the particular CEn active. This is the whole idea of "common bus" architecture: all I/O ports are listening to control signals and data, but only the one with CE active is responding.

ADDITION: look at the answer by Transistor. The IC U7:A is the base address decoder I am talking about. It generates two different CS (Chip Selects) for two distinct I/O chip.

Answer 3

I can think of a few ways to do this:

Use a demultiplexer with, say, the last 3 bits of the address bus as inputs, and then connect each output to the enable pin of a different PIO chip. The issue I see here is, how do I then use the A/B and C/D pins on the PIOs?

Use the first two bits of the address bus for A/B and C/D pins, and use the rest to indivually select each PIO chip. The issue here is that unless I'm careful whilst addressing the ports, I could enable two PIOs at the same time.

So long as you connect different address lines to A/B and C/D and each of the MUX address inputs it will be fine, even if the order is completely random. However some schemes can make programming easier and code more efficient.

Using A0 for C/D has the advantage of being able to switch between a PIO's control and data registers by adding or subtracting 1 from the I/O address, perhaps using INC C and DEC C or OUTI and OUTD instructions. This may save some instructions, making the code faster and more compact.

Using higher address lines for MUX addresses makes each PIO use a contiguous block of I/O addresses, vs being split between many address ranges. This doesn't affect operation in any way, but makes the I/O address map less confusing for designers and programmers.

If the I/O addresses are not 'fully decoded' then each PIO can be accessed at multiple 'mirror' addresses, but software only needs to know about the 'official' addresses.

Some commercial computer designs did not use a decoder at all, but simply connected a different address line to the /CE input each I/O device. If that address line was low then the device would be selected, but having more than one address line low at the same time would cause a bus contention and therefore was illegal. so the 'official' I/O map might look something like this:-

PIO 1 = 0x7F (A7 low) 
PIO 2 = 0xBF (A6 low) 
PIO 3 = 0xDF (A5 low)

This might seem dangerous because a software bug or glitch could cause multiple PIOs to be selected for reading at the same time, thus causing them to 'fight' for the data bus. However so long as only NMOS chips are used this is relatively safe, because the data bus drivers only pull low so they won't draw excessive current.