# Emitter-coupled logic operation

For the operation of emitter-coupled logic and sedra smith book,

1) Compared to CMOS, why ECL is the faster logic family given that it requires so many transistors to propagate to output Y (T5 emitter node) ?

2) Why current drawn from the power supply remains constant during switching and regardless of which input logical state the ECL is in ?

3) How is the reference voltage Vr made insensitive to temperature and PSRR according to calculation made below ?

• This sounds like homework. What do you think the answers are? – Edgar Brown Feb 21 at 4:55
• @EdgarBrown This is my personal homework. For question 2, I will do a LTspice simulation later today, I am not convinced with the wikipedia voltage/current illustrations on the transition and logical '1' and '0' states. As for question 1, I believe CMOS must be faster than ECL , right ? There must be some mistakes in the text ? – kevin Feb 21 at 4:57
• @kevin, 20 years ago, ECL was pretty unequivocally the fastest logic available. Today the fastest logic I know of is SiGe BiCMOS rather than CMOS or ECL. There may be CMOS that rivals ECL for speed, but generally only when used internally to a chip (where there the output loading is not too heavy). When driving across a circuit board trace, ECL generally remains faster than CMOS. – The Photon Feb 21 at 5:10

Compared to CMOS, why ECL is the faster logic family given that it requires so many transistors to propagate to output Y (T5 emitter node) ?

BJTs have the pleasing property that they react faster when operated at higher bias currents. This lets us tune BJT circuits to be very fast at the expense of consuming more power.

The ECL gate also maintains all the critical BJTs in forward active mode regardless of the digital input or output level, rather than fully switching them into saturation mode as in TTL gates, again resulting in higher speed.

Why current drawn from the power supply remains constant during switching and regardless of which input logical state the ECL is in ?

Since the gate and the outputs are differential, whenever one output goes high (increasing output current and supply current), another goes low (decreasing output and supply currents).

How is the reference voltage Vr made insensitive to temperature and PSRR according to calculation made below ?

According to the Motorola MECL Design Handbook (I found it here, but it's probably better to just google "MECL System Design Handbook")

The diodes in the voltage divider line [D1 and D2] together with Q6 [T3 in your diagram], provide temperature compensation by maintaining a level consistent with the midpoint of the logic levels despite changing temperatures.

I'm not 100% what Sedra & Smith have in mind here, but you can see that the reference node is the output of a voltage divider with ~1 kohm pull-up and 5 kohm pull down (plus the low-impedance diodes in series). So if Vee changes, the reference voltage will only change about 1/6 as much.

• What about PSRR insensitivity ? – kevin Feb 21 at 5:13