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I am trying to design an amplifier and low pass filter circuit for a piezo sensor.

My frequency of interest is .3 Hz to 5 Hz, for first stage I have used charge amplifier and the subsequent 3 stages in combination is 6 order low pass filter.

For initial few minutes the response is fine (as desired) but after sometime signal dies off and there is no result at any of the stage.

Input supply is 5V and Vdd reference voltage is 3.3V. enter image description here

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  • \$\begingroup\$ What is the voltage on left side of R2? Did the piezo destroy that first opamp? \$\endgroup\$ – analogsystemsrf Feb 21 '19 at 10:59
  • \$\begingroup\$ Its 3.2V due to Vdd The output from piezo is few millivolts i.e around 20-30mV \$\endgroup\$ – Sagar Feb 21 '19 at 11:07
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    \$\begingroup\$ Sounds like one of the amplifiers enters saturation. Maybe lower R1 (that resistor also serves to bleed the charge off capacitor C1)? \$\endgroup\$ – Huisman Feb 21 '19 at 11:12
  • \$\begingroup\$ I agree with @Huisman, what you can do to find the point is the measure all the DC voltages at the outputs of the opamps. Keep the input signal (piezo sensor) as small as possible). Then compare the working/now working DC voltage values. \$\endgroup\$ – Bimpelrekkie Feb 21 '19 at 11:16
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    \$\begingroup\$ Stage IC1A is perilously close to its common-mode upper limit of 1.5V...(yours is @ 1.7V with no input signal). Can your input signal exceed 0.2V? Also, it is dangerous to bias the shell of that jack at any other than ground - you risk the DC supply and microcontroller. Do not forget that the jack's tip can momentarily contact the shell as you plug-in. \$\endgroup\$ – glen_geek Feb 21 '19 at 13:46
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I guess some capacitor charges slowly and some part of your circuit drifts finally to the max or min voltage which the power supplies allow. You should find where the drift happens - check Vdd stability and separate the stages (=disconnect the left ends of interconnecting resistors and connect them to Vdd).

There's missing or too high resistance DC path somewhere. Or an electrolytic capacitor is used with wrong polarity.

Also your opamp IC can be faulty and gets gradually hot somewhere in the chip.

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  • \$\begingroup\$ I am using all ceramic capacitors. Second, times when circuit works the base or no input voltage at first stage is 3.2v, at second its 3.2v and at third, fourth its 1.2v. \$\endgroup\$ – Sagar Feb 21 '19 at 11:35
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It’s hard to know what the actual issue is but I see three red flags with your circuit.

  • You are directly driving the input of an Op-amp without any ESD protection or current limit. Furthermore one of its inputs is at the supply rail, some op-amps don’t behave reliably under those conditions.

It’s possible that the input node slowly drifts until that op-amp is out of range.

  • There is Vdd and a V+ label in your supplies.

Given the connections, and without knowledge of the rest of the circuit, it is possible that your op-amp is being powered through the ESD diodes. That would not be a very stable condition.

  • You have quite a bit of gain in Sallen-Key filter stages.

These types of filter quickly approach instability if the gain is too high. Gains >2 are somewhat rare. You should make sure you are not too close to the edge, where just temperature or offset drifts could put it out of bounds.

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