RAM Row and Column Decoders

I keep seeing similar diagrams of RAM like this abstract picture of a simplified RAM Layout. So I just arbitrarily selected this picture but my question is about this layout in general. My understanding is that the whole selected row sends their memory contents down their column lines and the column decoder selects the appropriate one to output. So is this understanding correct? And is the Row Decoder implemented by a decoder-like a 3 to 8 decoder- and is the Column Decoder a multiplexer? And are each of the column lines a bus? Is this how most RAM works in the big picture, for both SRAM and DRAM?

• Yes and no. I believe that some SRAMs may have different organizations. Certainly the DRAM organization is as you surmise. This is, to some extent, where burst mode comes from -- the read operation on a row takes time, but shuffling the right bit out of the column decoder is quick. Even the earliest DRAM would let you do a read on a row, then read different columns within that row without re-doing the row operation. – TimWescott Feb 21 at 21:04

The row address decoders are not implemented like a regular decoder; the layout of such a decoder would not be very efficient. Instead each row has a decoder that is basically a dynamic NOR gate. It consists on $$\N\$$ NMOS transistors in parallel, where $$\N\$$ is the number of address lines to be decoded. The true and complement value of each address line is routed over the top of the decoders...vertically, as your graphic is drawn. Since a NOR is also a NOT-AND we can selectively connect the gate of each NMOS transistor to either the true or complement of one address bit. The output of the decoder is where the NMOS drains connect together, and this is precharged before an access.