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I keep seeing similar diagrams of RAM like this abstract picture of a simplified RAM Layout. So I just arbitrarily selected this picture but my question is about this layout in general. My understanding is that the whole selected row sends their memory contents down their column lines and the column decoder selects the appropriate one to output. So is this understanding correct? And is the Row Decoder implemented by a decoder-like a 3 to 8 decoder- and is the Column Decoder a multiplexer? And are each of the column lines a bus? Is this how most RAM works in the big picture, for both SRAM and DRAM?enter image description here

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  • \$\begingroup\$ Yes and no. I believe that some SRAMs may have different organizations. Certainly the DRAM organization is as you surmise. This is, to some extent, where burst mode comes from -- the read operation on a row takes time, but shuffling the right bit out of the column decoder is quick. Even the earliest DRAM would let you do a read on a row, then read different columns within that row without re-doing the row operation. \$\endgroup\$ – TimWescott Feb 21 at 21:04
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Your understanding is basically correct.

The row address decoders are not implemented like a regular decoder; the layout of such a decoder would not be very efficient. Instead each row has a decoder that is basically a dynamic NOR gate. It consists on \$N\$ NMOS transistors in parallel, where \$N\$ is the number of address lines to be decoded. The true and complement value of each address line is routed over the top of the decoders...vertically, as your graphic is drawn. Since a NOR is also a NOT-AND we can selectively connect the gate of each NMOS transistor to either the true or complement of one address bit. The output of the decoder is where the NMOS drains connect together, and this is precharged before an access.

The column decoder is a selector...it selects a subset of all of the column lines. The column lines, or bit lines are single bits, not buses.

This is the general architecture for any kind of memory device. We like to make the core, the 2D Storage Array, have a relatively square shape. This is because the RC delay of the word lines and bit lines is proportional to the square of their length, so we don't want either of these lines to be really long.

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  • \$\begingroup\$ Since the column lines are single bits, then is it just bits being stored in this 2d storage array? Do you use 8 of these 2d storage arrays to store a byte? What do you mean by column decoder selecting a subset? Sorry I've only taken a basic digital logic course so I'm not understanding a lot of this. Maybe it's beyond my current reach. \$\endgroup\$ – Jaull Feb 21 at 21:48
  • \$\begingroup\$ It is just bits being stored, but the storage array may be 64 or 128 bits wide...so there are 64 or 128 column lines. If you just want one byte out of the memory then the selector must choose which of the column lines you care about, based on some of the address bits provided. \$\endgroup\$ – Elliot Alderson Feb 21 at 22:38

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