4
\$\begingroup\$

I am designing a PCB with analog signals for the first time, and I would really appreciate any feedback on my layout and routing.

The circuit is a light-meter, consisting of a photodiode connected to a transimpedance amplifier which connects to an ADC.

I simulated the transimpedance amplifier and put it on a breadboard, and it worked, but I am nervous about moving to a PCB. I based my layout on a TI reference design (http://www.ti.com/lit/ug/tidu535/tidu535.pdf), with a keepout on the top and bottom planes. I tried to make the amplifier output as close to the ADC pin (pin 16) as possible, and I tried to set up pin 18 as the single ground connection to my analog corner. Can you think of anything I could do differently?

The top layer of the transimpedance/analog section: transimpedance amplifier layout top layer

The bottom layer of the transimpedance/analog section: transimpedance amplifier layout bottom layer

The relevant portion of the schematic: enter image description here

Note: my transimpedance amplifier seems to be stable without a feedback capacitor. I think it's because my op-amp has a GBWP of just 6kHz and my large-area photodiode has a capacitance of 1nF. It has worked in simulation and on a breadboard and has a stable output with feedback capacitors between 0-100pF.

Edit: added links to the datasheets.

\$\endgroup\$
7
  • \$\begingroup\$ Why do you change the layer with your SDA and SCL signals? For me it seems like these 4 vias are unecessary. And why do you have your bottom layer cut out in the upper right corner? \$\endgroup\$
    – po.pe
    Feb 22, 2019 at 9:33
  • \$\begingroup\$ Forget about the 2nd question... \$\endgroup\$
    – po.pe
    Feb 22, 2019 at 9:44
  • \$\begingroup\$ May not be an issue in this case but I would lay out the board with pads for a feedback capacitor, just in case. The photodiode capacitance detracts from stability, of course. \$\endgroup\$
    – Spehro Pefhany
    Feb 22, 2019 at 9:55
  • \$\begingroup\$ The GND connection to pin 13 is not optimal. Currents have to go a "long" way on the right side of your board down to the GND pins near the battery to dive into the GND plane on the bottom. Put 2 or 3 vias near pin 13. Would be better to connect pin 13 directly to the GND plane under the WiFi. You need to get rid of the factory reset trace. Could you connect this signal to another GPIO maybe on the left side of the module? \$\endgroup\$
    – Batuu
    Feb 22, 2019 at 10:24
  • \$\begingroup\$ I routed the SDA and SCl paths on the bottom of the board because I wanted to keep the 3.3V plane on the left hand side as unbroken as possible. I can definitely change the factory reset trace GPIO - is it okay to run it between the SDA and SCL traces? \$\endgroup\$
    – Zach Morris
    Feb 22, 2019 at 16:30

1 Answer 1

Reset to default
1
\$\begingroup\$

Can you think of anything I could do differently?

Yes, I can think of one thing. Start learning how to model PCB parasitic component values. This takes some of the mystery out of PCB design and allows one to design circuits without worrying what the PCB will do to the design.

A PCB trace actually looks like this: enter image description here
Source: https://www.ecnmag.com/article/2017/06/plague-parasites

Whenever you add a pcb trace between two points, your adding a small amount of inductance and capacitance. The PCB trace has capacitance between it and the conductor below it (any two pieces of conductors\metals can be modeled as a capacitor).

enter image description here
Source: https://www.ecnmag.com/article/2017/06/plague-parasites

Just glancing at the schematic, I see it more like this after layout on the PCB. Each trace adds milliohms of resistance an nH of inductance. Inductance slows electrical signals down so making the traces small is a good idea because it minimizes inductance and resistance. enter image description here

The biggest problem I see is the ground of U1 and , with the small trace size, this is creating inductance and resistance on the ground of U1. If the signals of U1 are changing very fast (10's of MHz), you might have a problem with common mode noise on U1 because of the inductance of the two vias. While its great that you chose to route the ground of U1 to be the same of the photodiode, you might be able to rotate U1 and route the ground continuously on the top layer.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge that you have read and understand our privacy policy and code of conduct.

Not the answer you're looking for? Browse other questions tagged or ask your own question.