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If I have a USB Host Controller that supports USB 3.1 Gen 1 plugged into a hub, and 2 storage devices connected to the downstream ports, if I transfer data from one storage device to the other through the hub will the speed be 5 Gbps or 2.5 Gbps? I understand that USB 3.1 Gen 1 has full duplex communication, but I'm not sure how that will interact with the host controller.
If the speed is indeed halved, is there any way of increasing it short of finding a host controller with 2 USB ports?
The hub to upstream computer will be capped at 5 Gbps. You can do 5 Gbps to one of the two devices at a time, or 2.5 Gbps to both devices simultaneously.
If you want to move data from one downstream hard drive (A) to another downstream hard drive (B), what you're really doing behind the scenes is reading data from hard drive A into host computer RAM, then writing from RAM to hard drive B. I don't think you can write directly from Hard Drive A to Hard Drive B with just a USB hub; you need some processor in the chain to tell the data where to go.
This will limit you to 2.5G Gbps reads from Hard Drive A and 2.5 Gbps writes to Hard Drive B, because the hub's max data rate is 5 Gbps total.
I don't think you can speed this up without using a second USB host controller on your upstream host computer. If Hard Drive A and Hard Drive B are both connected to a laptop directly, over two separate USB 3.1 hosts, then you could hit 5 Gbps reads from A and writes to B at the same time. The USB hub does create a bottleneck in your data rate.
This is a good question. The answer depends on particular implementation and IP generation of host controllers. In theory, in full duplex, one drive can read data at 5 Gbps, and another drive can write the data at the same 5 Gbps. The bottleneck here may (or may not) be on host controller side, in interface between the main memory (which PCIe is used), MAC, and USB PHY, so called PIPE interface, see this conceptual overview on SE.OF
If you examine, for example, the Cadence IP offering for USB 3.x PHY, it has two 32-bit busses for Tx and Rx in parallel.
So in theory the interface is capable to transmit 5 GBps in both directions at the same time.
Each generation of PC platforms introduces some innovations in interconnect topology, new versions of interconnect IP are being introduced and implemented and tried by CPU manufacturers. I believe that recent implementations of xHCI controllers and PHYs have enough bandwidth to handle more than 10 Gbps internally, even if the production PHY is proven to work at Gen1 speed only.
The limitation however could be on conservative software end, or in some other glitches on ring buffer control side. This question is about extreme performance, and fringe performance issues are usually on the bottom of the list to debug.
