This is a good question. The answer depends on particular implementation and IP generation of host controllers. In theory, in full duplex, one drive can read data at 5 Gbps, and another drive can write the data at the same 5 Gbps. The bottleneck here may (or may not) be on host controller side, in interface between the main memory (which PCIe is used), MAC, and USB PHY, so called PIPE interface, see this conceptual overview on SE.OF
If you examine, for example, the Cadence IP offering for USB 3.x PHY, it has two 32-bit busses for Tx and Rx in parallel.
So in theory the interface is capable to transmit 5 GBps in both directions at the same time.
Each generation of PC platforms introduces some innovations in interconnect topology, new versions of interconnect IP are being introduced and implemented and tried by CPU manufacturers. I believe that recent implementations of xHCI controllers and PHYs have enough bandwidth to handle more than 10 Gbps internally, even if the production PHY is proven to work at Gen1 speed only.
The limitation however could be on conservative software end, or in some other glitches on ring buffer control side. This question is about extreme performance, and fringe performance issues are usually on the bottom of the list to debug.