Suppose a MOSFET gate-driver IC has only ONE ground pin. Suppose the input logic-level signal has ESD diodes to that Ground pin. Suppose the gate-driver is switching 10 amps in 10 nanoseconds, and the total inductance in the Ground path is 5nanoHenries. What happens?
V = L * dI/dT = 5nH * 10amp/10nanoSecond = 5volts.
Thus the ground pin will be rising 5 volts above ground on one output edge (the high-voltage swing), and will be falling 5 volts BELOW ground on the other output edge.
With the ground pin (attached intimately to the onchip "ground" metallization running all around the silicon) falling 5 volts below ground, the ESD diodes will be turning on, and vigorously pulling down on the logic-input signal. When pulled low enough, that logic-input signal will turn on the ESD structures in the MCU, injecting charges and upsetting the substrate/VDD of the MCU.
Thus the design/choice/methods/approach of ESD structures is a proprietary and competitive advantage for those companies in the gate-driver business.
Examine the power-driver datasheets. Some will discuss their wide input tolerance of Ground Upsets, such as "tolerate input logic-level signals that are at -5/-6/-7 volts". This is a way of saying there is NOT A NORMAL DIODE performing the ESD diode behavior, but some more interesting ESD method.
Other datasheet may be silent about problems with ground movement that exceeds +- 0.6 volts.
Again, for standard ESD diode clamps, the huge movement of the PowerDriver ground will INJECT huge currents into the MCU if directly connected to the PowerDriver IC.
SOLUTION? Assign 2 pins to the "GROUND" function: (1) as reference for the logic-level input; (2) as return path for the 1 amp or 5 amps or 10 amps output current.
Notice the above computed rail-ringing slewrate --- 1 volt per nanosecond ---imposes a severe burden on the gate-driver's internal logic-level interface for PowerSupplyRejection.
Both the high current return (GND) and the high current input (VDD) will be ringing. On poorly chosen IC packages and poorly designed PCBs and poorly designed FET loads (and FET wiring and PCBs), you can easily get another 5 or 10 volts ringing, superimposed on the VDD.
DILEMNA What if the chosen wafer process is standard Nwell (the PFETs are implanted inside an Nwell). This means the substrate is Ptype, and the NFETS are implanted directly onto the substrate; this means the NFETs for the logic-level interface and the NFETs for the high-current (high ringing) are at most only one diode-drop (the source_substrate isolation diode) apart for their "isolated grounds".