Looking at the datasheet for the MC74VHC1G08, under the features section, it states Chip Complexity: FETs = 62.

  • Why does this IC need 62 transistors, while an AND gate can be made with only 6 transistors?
  • What are the other 56 transistors being used for? My guess would be some sort of protection circuitry, but I am not sure.
  • 10
    \$\begingroup\$ How can you make a CMOS AND gate with two transistors? I need a minimum of six, and I need a bunch more to buffer the output to drive a big off-chip load. \$\endgroup\$ Feb 22, 2019 at 21:09
  • 1
    \$\begingroup\$ Does it actually have 62 transistors, or does ON have some formula to calculate sizing (like "tax horsepower" in the old days, only in the other direction)? Are all the transistors independent, or does it have a bunch of parallel transistors on the output for fan-out? \$\endgroup\$
    – TimWescott
    Feb 22, 2019 at 21:15
  • 4
    \$\begingroup\$ There might not be literally 62 transistors; this might be a "normalized" number that gets plugged into some sort of reliability-predicting midel. That said, the datasheet says that it has "multiple stages", including an output buffer. And yes, input protection would count towards the transistor count, too. \$\endgroup\$
    – Dave Tweed
    Feb 22, 2019 at 21:18
  • \$\begingroup\$ @ElliotAlderson You're right - that should say 6, not 2. \$\endgroup\$
    – eeze
    Feb 22, 2019 at 21:36
  • 4
    \$\begingroup\$ @Platytude I don't pretend to fully understand why, but I've heard diodes in CMOS are sometimes implemented using FETs. Maybe doing everything possible with FETs makes the fabrication process easier or something. \$\endgroup\$
    – mbrig
    Feb 22, 2019 at 22:31

5 Answers 5


There can be several reasons why more than the minimum 6 MOSFETs (4 for an NAND + 2 for an inverter) are used in this IC:

  • As stated in the datasheet:

The internal circuit is composed of multiple stages, including a buffer output which provides high noise immunity and stable output.

  • The output will be made using fairly large (not minimum size) transistors. There are always "folded" meaning multiple transistors are combined into one large one where drain and source diffusion areas are shared between two transistors. This behaves as one large transistor but could be counted as many if you want a higher transistor count.

  • The ESD protection at inputs and outputs of IC fabricated in modern CMOS processes often uses "grounded-gate MOSFETs" instead of the more traditional diodes.

  • An "ESD clamp" circuit is needed between the supply pins, such a circuit consists of a couple of transistors.

  • Digital circuits (like this AND gate) often need on-chip supply decoupling. These are called "decap cells". These are capacitors between the supply rails. These capacitors are mostly made by using the Gate-Drain/Source capacitance of Transistors.

  • In CMOS processes the MOSFETs are the most "basic" components, they are also the most controlled component and most flexible ones so IC designers prefer to use a MOSFET whenever possible.

All-in-all it is "quite easy" to need 62 transistors to make a seemingly simple function like an AND gate. That's also because this IC is "a bit more" than just a simple AND gate. The AND gates in more complex circuits like CPUs, microcontrollers etc. will often only use 6 transistors. But these aren't "stand alone" AND gates like this IC.

  • \$\begingroup\$ Is there a reason why you wouldn't just fab a larger transistor on the die instead of using multiple, smaller ones in parallel? \$\endgroup\$
    – DKNguyen
    Feb 22, 2019 at 21:57
  • 4
    \$\begingroup\$ @Toor Yes, the size of the transistor. Say I need a W/L of 1000um/0.13um. That would mean a very wide ( 1mm) but very thin (less than 0.0005 mm) transistor which is unpractical, that would result in a very unusable size for the chip. What is preferred is a almost square chip (but a rectangle is OK as well). So we fold that transistor into for example 20 smaller ones of 50um/0.13um and combine that into a rectangular shape. Have a look at what that looks like here: zeptobars.com/en/read/… \$\endgroup\$ Feb 22, 2019 at 22:25
  • 1
    \$\begingroup\$ The "folded" output transistor of this LDO is the structure between those two "blobs" (those are the bonding pads) in the upper-right part of the picture. Although this is an LDO, it would look similar on any IC where large MOSFETs are needed. \$\endgroup\$ Feb 22, 2019 at 22:26
  • 2
    \$\begingroup\$ Ah, so it's so you can "pour the transistor" into all the nooks and crannies available on the wafer. Like pouring sand into a jar rather than filling it with a few large rocks and empty space. \$\endgroup\$
    – DKNguyen
    Feb 22, 2019 at 22:31
  • \$\begingroup\$ @Toor Correct, it's not as simple as pouring sand but the idea is indeed the same, it is much easier to fill a (randomly spaced) shape with small units that it is to efficiently fill it with a very long and narrow single transistor. \$\endgroup\$ Feb 23, 2019 at 12:43

From ON Semiconductor MC74VHC1GT00 - Single 2-Input NAND Gate Product Guide:

The internal circuit is composed of multiple stages, including a buffer output which provides high noise immunity and stable output.

The MC74VHC1G00 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the MC74VHC1G00 to be used to interface 5 V circuits to 3 V circuits.

Chip Complexity: FETs = 56

Power Down Protection Provided on Inputs

Balanced Propagation Delays

From ON Semiconductor MC74VHC1GT00 - Single 2-Input NAND Gate datasheet.

The input structures provide protection when voltages up to 5.5 V are applied, regardless of the supply voltage. This allows the device to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when \$V_{CC}\$ = 0 V and when the output voltage exceeds \$V_{CC}\$. These input and output structures help prevent device destruction caused by supply voltage − input/output voltage mismatch, battery backup, hot insertion, etc.

\$I_{OFF}\$ Supports Partial Power Down Protection

ESD Withstand Voltage > 2000V

We have at least three stages, which are input, logic and output.

The MC74VHC1G08 AND gate, which can be formed from a NAND and a NOT, takes 62 FETs. The MC74VHC1GT00 NAND takes 56. Same family, so approximately 6 FETs to implement an inverter. Which would mean the MC74VHC1G00 would have around 9 gates of functionality and the MC74VHC1G08 10 gates.

The basis of the OP's question is an AND logic can be implemented from 6 gates, but a NOT in a MC74VHC1G08 must be at least 6 FETs.

Say 8+6 to implement the logic, which would leave around 48 FETs to provide all the extra protections.

Guess 5/6 FETs/input to provide ESD protection = 36 FETs.

The rest to provide all the other protections. This is clearly not a simple AND gate.


How many paralleled little MOSFETs are in one power MOSFET? Thousands? This little gate has a fairly high output current, so it needs 62 tiny MOSFETs to do it.

My two cents worth of a guess.


The harder the gate of a MOSFET is driven to turn it on, the longer it will take for the MOSFET to subsequently turn off. Performance may be improved by adding circuitry to limit excess gate voltage, though doing this without increasing quiescent power dissipation is tricky.

I don't know what exact techniques are used in CMOS to prevent oversaturation, but low-power Schottky devices based on bipolar junction transistors may provide a useful analogue. Consider the two simple inverters shown below:


simulate this circuit – Schematic created using CircuitLab

The inverter on the left is simpler than the one on the right, but if one runs the simulation, one will see that the adding the diode allows the circuit on the right to switch off much more quickly than the one on the left.

In the BJT-based inverters below, the Schottky diode will slightly increase the power dissipation in R3, but such increase will be tiny compared to overall power consumption. In a CMOS device, simply clamping the gate voltage would increase power dissipation, making it necessary to use other, more sophisticated, approaches.

  • \$\begingroup\$ I don't recall MOS having charge-storage slow-down behavioral issues. \$\endgroup\$ Feb 23, 2019 at 4:45
  • \$\begingroup\$ For small MOSFETs, adding extra circuitry to bias things optimally probably isn't useful, but big MOSFETs are going to at minimum have gate capacitance, and I think they have other design issues beyond those, though I don't know exactly what they are. Using a four-transistor NAND gate feeding a two-big-transistor inverter (or even two big paralleled groups of transistors) would likely not yield as good performance as could be achieved with better control of gate voltages. \$\endgroup\$
    – supercat
    Feb 24, 2019 at 7:25

Maybe the die actually has four AND gates on it, because it's using the same exact physical die as this MC74VHC08 chip, just only wiring up one of the gates.

Why got to the cost and trouble of designing, testing and supporting a whole separate die, when the cost between 17 vs. 62 transistors on silicon is basically nil?

That would add up to 2 or 6 transistors to protect the power supply, and 14 or 15 transistors per AND. Not so unreasonable.

  • \$\begingroup\$ Wondered about that too - it's not a crazy idea as most power consumption would be dynamic so the unused gates would be hard to object to. However your link to the datasheet for the quad part says "Chip Complexity: 24 FETs or 6 Equivalent Gates" - ie, simpler. \$\endgroup\$ Feb 24, 2019 at 17:30

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.