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I am using a Altera MAX V CPLD. When I try to program the CPLD using QUARTUS II, it is reading the device ID and silicon ID correctly, but it failing during verification. I tried to isolate the signals around TDO and TCk to see if noise was affecting the signals with no change.

Is there anyway, I Could reduce the TCK frequency for programming CPLD in Quartus II? Are there any other 3rd party programming tools which I could use to program the .pof file generated from QuartusII?

Thanks, Vijay

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    \$\begingroup\$ Ok first what blaster are you using is it the Terasic one? That one gives us all kinds of problems. When examined the difference between the true Altera Blaster and the Terasic I found Terasic used a weak level shifter instead of a line driver on their outputs. You can even see the difference in level on a scope. Anyway I wired in a driver and things worked much better. So try a real Altera Blaster if you have one. I've never seen a way to lower the frequency. \$\endgroup\$
    – Some Hardware Guy
    Commented Sep 30, 2012 at 14:24
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    \$\begingroup\$ Oh and you might try looking at the jtag signals on a scope, you may see that changing your termination pull up or adding a series terminator might help you get your signals through. \$\endgroup\$
    – Some Hardware Guy
    Commented Sep 30, 2012 at 14:27

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Altera provides source code for something they call a Jam STAPL player. If you build it with an I/O implementation that is slower than intended, it will work but program things more slowly.

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If the signal on your TCK line is not clean, reducing the clock rate won't help - the edges have to be monotonic first.

Probe the JTAG signals with a high bandwidth scope and check they are OK.

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