I am using a Altera MAX V CPLD. When I try to program the CPLD using QUARTUS II, it is reading the device ID and silicon ID correctly, but it failing during verification. I tried to isolate the signals around TDO and TCk to see if noise was affecting the signals with no change.
Is there anyway, I Could reduce the TCK frequency for programming CPLD in Quartus II? Are there any other 3rd party programming tools which I could use to program the .pof file generated from QuartusII?