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For STM32F405 the max system clock frequency is 168 MHz. I want to run it at marginally lower frequency only for the sake of safety and reliability because my application will run non-stop through out a year without going into low power sleep mode. Should I select a value for SYSCLK or HCLK as a power of 2 (example 128 MHz) or can I select any value (example 150 MHz or 148 MHz etc)?

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Edit:

Jitter info added below:

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Any frequency is allowed, CubeMX won't allow illegal values. However if you use a peripheral that needs the 48Hz clock then than must be set correctly too. What may be important is the input range to PLL, with some values there is less jitter. Read the data sheet about PLL input.

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    \$\begingroup\$ Ok, you mean 48MHz. \$\endgroup\$ – scico111 Feb 23 at 8:47
  • \$\begingroup\$ I have read the details about PLL characteristics and added the table in the question now. But I cannot find information how to find the values which give less jitter. Do I have to do it by experimentation? \$\endgroup\$ – scico111 Feb 23 at 21:53
  • \$\begingroup\$ If you want to test that is fine. In fact it reads in the Reference Manual. Typically the PLL input is 1 MHz by default anyway and that is good enough for most things (except the PLL output jitter always exceeds Ethernet specifications so it should not be used for that). \$\endgroup\$ – Justme Feb 26 at 10:31
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The PLL appears to be performing an integer divide, so the only significant parameter is the ratio between the reference clock and the output. Unless you're concerned about high bandwidth communication, the level of jitter which you can expect should be ittelevant to your application.

Unless the datasheet says otherwise, device ageing is not significantly affected by operating frequency. Supply voltage, heat dissipation - yes, 10% clock speed backoff not so much. Even overclocked you would be unlikely to observe a significant degredation over time in achievable frequency. Clocking of these devices is delay limited, not thermally limited.

To expand on the latter point, timing between registers is the limiting factor for power/area optimised designs. So in the M4 CPU, there are maybe up to 25-35 levels of logic (nand2) between typical pipeline registers. Depending on the technology, this determines fmax through propagation delay. Faster cores have longer pipelines (less logic in each stage), and do the same work over more clock cycles (trading throughput for latency).

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  • \$\begingroup\$ This is very helpful. Please tell more about what is your meaning by 'delay limited'? \$\endgroup\$ – scico111 Feb 28 at 3:30
  • \$\begingroup\$ Timing between registers, So in this design, there are maybe 25-35 levels of logic (nand2) between pipeline registers. Depending on the technology, this determines fmax through propagation delay. \$\endgroup\$ – Sean Houlihane Feb 28 at 7:25

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