# How to remove leakage current from nRES transistor switch?

I have this AVR reset pin design, which provide a 12V into the nRESET pin of an ATtiny μC. It's function can be describes as follows.

• (a) An input signal given by a "low" (0) on J2-1 lets a current flow through LED to show it is "ON", while at the same time pulling the T1 base "low", thus effectively removing T1 from circuit and providing 12V from battery into nRESET.

However,

• (b) An input signal given by a "high" (1) on J2-1 would turn "OFF" the LED, while at the same time pulling the T1 base "high", enabling T1 and feeding 12V to GND via R1 (1K) and pulling nRESET "low".

Here is the schematic.

What is the problem?
Battery drainage of 12 mA, when the nRESET signal is not needed, or signal input or power is not connected.

How can I improve the circuit to not drain the battery when the reset signal is not needed/used?
(Preferably with minimal number of added components and using cheap off-the-shelf ones.)

BTW. Is there still a Voltage drop when 12V is not grounded?

References:
I've also looked at a few similar posts and solutions using MOSFETs, but they are either not helpful or I don't understand them, as I'm not clear how to apply the differences, and how to understand the many variations of the MOSFETs available.

• No significant load on nRESET
• Some (internal?) pull-up/down R may be present on nRESET side
• 12V Battery may be replaced by ~12V DC source
• HVSP_ON signal may be 5V or 3.3V

UPDATE-1:
Since I was told that the type of circuit to search for is called a High-Side Driver, I now see these everywhere, with thousands of variations. I choose to accept Turbo's answer because his diagram provide a very nice flow of higher voltages to GND from top to bottom, and signal flow from left to right.

UPDATE-2:
I tried the Tubo's circuit in LTspice, but there seem to be a problem with the MOSFET never shutting down 12V. I tried several different components. Any ideas why this doesn't work?

Where:
Green - nRESET
Blue - V1
Red - Q1:B

UPDATE-3:
Added a load resistance R3 via GND to $$\\overline{RESET}\$$, so now it works.

• "Danish" added this comment as an edit - The circuit does not drive the output actively to zero volts. It either drives 12V or nothing at all (left floating). (I just noticed that my comment from yesterday is not entirely correct, it doesnt drive 0V at all, not even through the parasitic body diode and the other mentioned components) In Order to fix this, you can try to add a Pulldown Resistor from ´nRESET´ to Ground or Vcc (depending on whether you want it to be in the Reset state or running). 10k should be fine. – Swanand Feb 25 '19 at 15:17
• Yes, adding a load to GND, fixed the issue. I also tried to simulate this in Falstad, but the poor implementation of MOSFETs make the results unusuable except when you set $V_{th}$ and $\beta=0$. – not2qubit Feb 25 '19 at 17:34
• I now got this model to work in falstad, the problem was bad default values for p-MOSFET, but manually editing the $V_{th}=-3.5$ and $\beta=80$ now give the correct behavior. – not2qubit Feb 26 '19 at 10:16

AVR reset pin design, which provide a 12V into the nRESET pin of an ATtiny μC.

Re-read the manual. The nRESET pin of an AVR has three states:

• 12V for HVPP only
• GND for Reset/ISP mode
• Pulled to VCC via internal or external 1k..10k resistor for normal chip operation

Your circuit above only supports the first two (12V and GND) states.

The 12V HVPP mode is usually only used to recover from wrong fuse settings, so it can be completely omitted in most designs. You will need another programming method (ISP or PDI depending on chip type).

In case one really needs HVPP, a proper high-side switch is strongly recommended, for example:

simulate this circuit – Schematic created using CircuitLab

Above circuit won't consume any current above transistor leakage levels when HVPP_On is low.

The MOSFET I'm used here is a 20V P-chan MOSFET, because battery can be a bit above 12V.

• Thanks Turbo, this look very promising! And I appreciate the great logical flow of your schematic, where voltage goes from top to bottom, and signal flow from left to right. However, two questions: (1) How did you determine what the R values should be? (2) Can HVPP_On be left floating? – not2qubit Feb 25 '19 at 8:23
• HVPP_On should not be left floating, for EMI reasons. Electromagnetic niose from the environment (or the rest of the circuit) could briefly turn on T2 - you don't want that. – Turbo J Feb 25 '19 at 21:39
• Thanks. I also noticed that it may be better to put LE(D1) between R2 and T2 to avoid a 0.7V diode drop on the nRESET output, unless it has another function I should know about. – not2qubit Feb 25 '19 at 23:02
• Nope. That Diode is there to prevent overvoltage on the MOSFET gate, which is specified for 12V absolute maximum. The nRESET will only ever see the R_DSon voltage drop across the mosfet (or it will be high impedance). – Turbo J Feb 25 '19 at 23:15
• Please keep in mind that the source is the reference point for gate voltage (V_GS). And source is fixed at +12V. – Turbo J Feb 26 '19 at 16:06

You may simply increase the value of the topmost 1kΩ resistor to 10kΩ or even 100kΩ.

If the circuit on the right, that uses the nRESET signal, needs low impedance output, you may add a CMOS non-inverting buffer.

• This could also be a good idea, but I'm not sure how that would affect the case scenario where you are attaching nRESET to an already populated board with other components possibly interfering with the pull-up/down R's. – not2qubit Feb 24 '19 at 22:06
• @not2qubit I think you should first know what is connected to that nRESET signal on the already populated board. Once you know it, you may think about the best way to drive this signal as needed. – user2233709 Feb 24 '19 at 22:18
• @not2qubit It depends on what is connected to that nRESET signal, but my guess is that the circuit suggested by Turbo J is probably more appropriate. – user2233709 Feb 24 '19 at 22:24