I am trying to incorporate a CMOS SR latch made with 180nm Level +49 transistors into a larger circuit but am running into issues. I am hoping this community can point me in the right direction of possible solutions.
First, I made a CMOS NOR gate with the transistor model in xyce (an open source circuit simulator) and built them into an SR latch. I was able to get the NOR gate and SR latch working, or so it seems. I used the following configuration exactly as shown.
This is the SR latch behavior for the SR latch I built with the transistors: (I am using matlab to read the csv outputs)..
And this is the behavior for a xyce SR latch built with ideal NOR gates
I also want to include some parameters I am using for the SR latch made with ideal NOR gates in case they ring a bell for anyone..
* Ideal NOR gate default parameters: .param R1HI=5 R1LO=200 R0HI=200 R0LO=5 RIN=1000 R1=100 .param SW=5.e-9 CAPOUT=1.e-12 CAPIN=1.e-12 *SR Latch Digital model card .model DMOD DIG ( CLO=CAPOUT CHI=CAPOUT + S0RLO=R0LO S0RHI=R0HI S0TSW=SW + S0VLO=-1 S0VHI=1.1 ;logic margins LOW + S1RLO=R1LO S1RHI=R1HI S1TSW=SW + S1VLO=1.7 S1VHI=1.9 ;logic margins HIGH + RLOAD=RIN CLOAD=CAPIN + DELAY=2ns )
I built these and tested them in separate files even using the same node names.
However, when I incorporated them into the larger circuit, the ideal SR latch worked in unison with the larger circuit as expected, but the CMOS latch had erratic behavior with no distinguishable pattern. The simulator still generated output but the behavior was not at all what was expected. The CMOS SR latch stopped resembling an SR latch, as far as I can tell. This is strange because they both had pretty much identical behavior in their respective simuations (save for the pullup time on the ideal latch).
- Are there any modifications to the CMOS circuit that could resolve an issue like this?
- What test could I perform on the SR latch, nor gate, or nmos/pmos transistor to see what is causing this difference in behavior?
- Kind of following up on the first bullet point, when building gates out of transistor models like these, should I include external resistances/capacitances/etc to eliminate possible strange behavior? etc
Any help appreciated! I will do my best to clear up questions if there are any.