The design is based on the 74LS191N 4-bit Up/Down Binary Synchronous Counter.
In order to switch from "Up" to "Down" counting you must have the positive slope of the "Up/Down" occur during a "High" pulse on the Enable, all taking place during a high clock pulse (as also briefly described in the introduction of the datasheet).
Finally, shown below are the results of my transient analysis of the schematic where:
- Red = Clock
- Teal = DAC output
- Pink = Analog Signal
- Navy Blue = Enable pin
- White = Up/Down pin
I have achieved getting a positive-slope transition while the enable pin is high, during a positive clock pulse but the counter still refuses to count down. Any help?