# TTL square wave inverter adjustable duty cycle

I am an amateur and I don't have experience with logic circuits so please forgive me if this is very simple.

I have a 5V TTL crystal oscillator (4-pin). I need to create a second square wave from it that is 180 degrees out of phase with the first wave. It would be optimal to be able to adjust the duty cycle of the waves. (Just to note - this will operate at up to 20MHz)

I know I can probably use an inverter, but I have never made 'logic' circuitry before.

Depending on your requirements, you may have bitten off rather more than you can chew. For discrete logic, 20 MHz will be a real challenge, especially if you need the new waveform to be precisely 180 degrees out of phase. So the exact phase tolerance allowed is one of the things you need to specify.

CL s answer is a perfectly reasonable first approach, but be careful of that td which he so innocently includes in his diagram. For instance, if your Schmitt trigger is a 74HC132 operated at 5.0 volts Vcc, td is nominally about 11 nsec, and you should figure on a worst-case of about 20 nsec, with the actual number depending on exactly which chip you select. At 20 MHz, the period is 50 nsec, and the difference between rising and falling edges (assuming a 50% duty cycle, which you cannot do - in my experience, compact TTL oscillators typically have a 40 - 60% spec), or 25 nsec. As a result, it's entirely possible that your actual wave form will not be inverted at all.

In this case, I'd recommend using two of CL's delays in series. The second would be used to generate the output pulse with the desired width, and the first would adjust the phase delay of the output.

I would also recommend looking into faster logic families. Something like the 74AHCT132 would probably work.

Of course, there's another problem - you have not specified exactly what range of pulse widths you need to produce. Be aware that trying to produce pulse widths which are less than td is likely to end in tears.

Finally, if you're going to go to a fast logic family such as 74AHC/AHCT, you need to follow some rules. Without special techniques (line termination), you must not drive long signal lines. For AHC, this means nothing more than a couple of inches long, and 1 inch is better. You must use a ground plane, and you must provide good decoupling of the chip. For the proposed circuit, the RC component layout needs to be compact and as close to the IC as possible. Also, variable resistors for R, while tempting and convenient, may produce nasty surprises when you use them for this purpose. At these speeds, they simply don't behave like simple resistors.

• Thanks. I will likely never go above 16MHz, but I put 20 just in case. In terms of duty cycle 40% 60% is likely what I'll need, but having an adjustment of +-10% would be good. Feb 24, 2019 at 20:46

ONSemi's application note Pulse Generation and Signal Conditioning Circuits Using Configurable Multifunction Logic Gates shows how to delay the leading or trailing edge of a signal with a Schmitt-trigger gate and a RC delay, e.g.:

You can do this

simulate this circuit – Schematic created using CircuitLab

C4 varies the Delay. R10 varies the duty cycle. And you can select the polarity you want.

I'd suggest a fast analog comparator instead of building this. The diffpair is a crude replacement for such a comparator. Notice the VDD filtering: 1uF and 10 ohms. Expect to use similar VDD filtering for a fast analog comparator. (Avoid the LM111 types)