I have an internship coming up working with comparators and amplifiers, so I wanted to take on a side project involving both of those components. Designing a D-Class amplifier seemed like a great way to get some experience making a more involved pcb layout, but before that, I wanted to verify that my schematic is ok. Below is the circuit I came up with.
Inputs are a 1Vp-max audio signal from an audio jack and a 200kHz triangle wave. For the triangle wave I am planning on using a SN54LS624 VCO. Audio inputs are offset ~.1V in in order to cause dead time for minimization of shoot through current of the amplifier FETs.
For my PWM I'm using a pair of LT1819s, chosen for high slew rate and ability to handle 200kHz without issue.
For the gate drivers I'm using LTC4440-5, chosen for its voltage output range. I've never worked or learned about a gate driver prior to this, so it's possible that I'm grossly misusing it. High side driver ranges from -20 to 42V, while low side ranges from -20V to 4V. Is there a way to change this? I don't think it's necessary to bia my NMOS at 42/-20V, and doing so might damage them at worst or slow them down at best. Is this something I'm missing or is my design valid thus far? I know that dual high side and low side drivers exist, and can have built in dead time, should I consider using one of those instead?
Power MOSFETs are IPB136N08N3, chosen for Vds max of 80V, and Vgs max of +-20V. My high side gate driver biases with a Vgs max of 22V, yet another reason I think I'm messing that bit up.
Filter is a 3rd order low pass with a cutoff of 23kHz and attenuation of -45dB at 200kHz. Initially I had a 2nd order but was noticing a low signal to noise ratio at the lower input voltages (Input = 0.5Vp).
Project is planned to use two 20V 3.25A DC power supplies, using diodes for 5V and ~1V (1V for offset and potentially for tri-gen). I've never had any experience with power supplies, so this is another shaky area for me.
Other concerns are current spikes in the push-pull NMOS show below. I don't think it's a big deal as each spike is ~25-50ns long, so maybe that's just the simulation being really precise and wouldn't happen in reality but I'm not sure.
^Power dissipation on high side NMOS