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Our company has designed a board for a custom SoC network processor. It has a PCIe gen2x4 interface, with a PCIe PHY.

This PHY's PLL requires a 100 MHz reference clock. We are using the reference clock from host PC which is acting as RC and SoC is acting as EP.

We are able to lock PLL on some SoCs after doing some settings in the PHY registers and also able to get the link up (although linkup do not happen on 2x4 every time on the PC start up, but after enabling and disabling the LTSSM two or three times, it gets linked up to 2x4.), but some SoCs don't get locked with same register settings.

Then we reduce the bandwidth of PLL by decreasing the charge pump current. By doing this we are able to get PLL locked if PC is on and PLL is getting 100 MHz clock.

After this, we power off both PC and board.

Now for linkup we power on the board (EP) first and then PC (RC). But now PLL is not able to lock and therefore no linkup happens.

We have measured the RMS cycle to cycle jitter with SoC mounted on the board, in time domain which is coming around 18 ps.

PCIe gen2 spec says that RMS jitter should be around 3 ps. But they specify this jitter for some particular frequency range like 10 kHz to 1.5 MHz and 1.5 MHz to Nyquist (=Refclk/2).

  • So are we not meeting the specs or we have done the wrong measurement?
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  • \$\begingroup\$ Hm, no, that's not how jitter works: I think you might be simply misreading the specs. Can you refer us to where you're reading these "10 kHz to 1.5 MHz"? \$\endgroup\$ Commented Feb 24, 2019 at 19:41
  • \$\begingroup\$ @ Marcus : microsemi.com/document-portal/doc_view/… on page 5 bottom \$\endgroup\$
    – Amit
    Commented Feb 24, 2019 at 19:49
  • \$\begingroup\$ I'll have to agree with you – after having read the spec (PCIe Base Specification Revision 2.1, section 4.3.3.1) as referred to in that whitepaper (always read the original sources if possible!), they specify a frequency range-specific RMS jitter which makes me sigh a little, but OK. So, what they mean is that your phase noise needs low enough that if you, in the end, consider the filtered jitter, the RMS (which is essentially the standard deviation of that stochastic entity) is below 3 ps. 3 ps RMS jitter just doesn't make too much sense for a < 1.5 MHz signal... \$\endgroup\$ Commented Feb 24, 2019 at 20:28
  • \$\begingroup\$ When I read your post you have need to have a few goes locking the PHY PLL to the clock. Then you power it off and back on and it's again unlocked. So do you need to repeat your process ? Have you got a 100MHz signal generator you can connect into the PHY ? To rule out the PC. The datasheet may also have a sequence for the PLL getting lock. \$\endgroup\$ Commented Feb 24, 2019 at 21:15
  • \$\begingroup\$ @ Marcus If the bit rate is 1,500MHz and the loop bandwidth is 1.5Mhz, then that 3pS gets accumulated and becomes 3pS * sqrt(1,000) = 100 picoSeconds. \$\endgroup\$ Commented Feb 24, 2019 at 23:17

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Place a Spectrum Analyzer on PLL output, and examine the various frequency components causing the jitter. Then identify the sources. Then decide how to reduce the sources of the trash.

1) does your 100MHz Reference clock remain CLEAN? if interferers are linearly added to the 100MHz signal, then converted into a square-wave inside the IC, you will have increased edge jitter. Again, use a spectrum analyzer and identify the frequency components. You will need to account for up-multiplication and for down-division, in diagnosing the components.

2) is your VDD clean? some circuits (logic gates in particular) have ZERO (OK maybe 6dB) Power Supply Rejection. Thus 10 milliVolts of VDD trash, from the switching power supply, causes the zero-crossing point of logic gates to wander in time; thus jitter can be ADDED after the PLL, during logic-flipflop division ratios.

3) do you use Ground planes, to protect the signals? As the 100MHz Fref moves about the PCB, are there any slits under the trace? Does the trace run near a switching power supply?

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