I have 2 problems with diode clampers that I don't understand

First, in this circuit for example: In the positive half cycle, the voltage across the diode is the diode drop of 0.7 V

Then the voltage across the load resistance must be 0.7 V

Then isn't that a constant dc voltage? Why is it that when it gets clamped it appears as a sinusoidal peak? In which, the resulting shift happens like this: My second question is specified to this following example: Analyzing the positive half cycle, the diode is reverse biased, then the voltage across the load resistance should be zero ( Me assuming that the capacitor cannot fully charge instantaneously ) But this isn't the case, the input actually shifts by 14.3 V upwards.

To try to make sense of this, maybe they assume that the capacitor needs no time to charge, so it charges up to the peak of the input voltage V_p(in). But still there's a problem, that would produce a shift of 15 V upwards, not 14.3, then there must have been a voltage drop across the diode, but how did that voltage drop occur in the positive half cycle if it's reverse biased? Thanks.

• "Analyzing the positive half cycle, the diode is reverse biased, then the voltage across the load resistance should be zero" is wrong. The voltage across the load is not zero. Why do you think it has anything to do with the capacitor's state of charge? – DKNguyen Feb 26 at 2:48
• I'm sorry, yes you're correct, but still, if the diode is reverse biased, where did the diode drop occur? – khaled014z Feb 26 at 2:55
• diode drops 0.7V when conducting if current is reasonable – Tony Stewart Sunnyskyguy EE75 Feb 26 at 2:56
• The 0.7V is a FORWARD voltage drop for when the diode is forward biased and conducting current. When a diode is reverse biased and not in reverse breakdown, it is not conducting current therefore you just (ideally) treat it as an open-circuit so there is no voltage drop due to the diode itself. That means the diode drop across a reverse biased diode not in breakdown is entirely dependent on the circuit around it. The diode is uninvolved. – DKNguyen Feb 26 at 2:56
• Yes, but in the second picture, the diode is reverse biased in the first half cycle, and the graph shifted by 14.3 V, that means its new peak is 29.3 V, where did that 0.7 come from if the diode is reverse biased – khaled014z Feb 26 at 2:58

In the positive half cycle, the voltage across the diode is the diode drop of 0.7 V Then the voltage across the load resistance must be 0.7 V

Only for the first 90°. Figure 1. Vout is shown in red. This assumes that RL does not load the circuit significantly.

Then isn't that a constant dc voltage? Why is it that when it gets clamped it appears as a sinusoidal peak? In which, the resulting shift happens like this:

The second diagram you provided shows the output waveform after the first cycle. My Figure 1 shows the first two cycles. On the first 90° the input voltage rises but the output is clamped at +0.7 V. At that point the capacitor is charged to Vp so when the input voltage starts to fall the output falls too.

In most practical circuits RL will load the capacitor so the capacitor will discharge somewhat and the negative peaks won't be as low as I have drawn them. As a result the diode will have to clamp again on the next positive half-cycle and the top of the red curve will be a little flatter.

Analyzing the positive half cycle, the diode is reverse biased, ...

Correct.

... then the voltage across the load resistance should be zero.

Incorrect. If the diode is reverse biased you can imagine it removed from circuit. Therefore the voltage on the right follows that on the left.

To try to make sense of this, maybe they assume that the capacitor needs no time to charge, so it charges up to the peak of the input voltage V_p(in).

No. Have a look at my Figure 2. Figure 2. For the first half-cycle C is not charged so the output voltage follows the input voltage. Between 180° and 270° the input is going negative so the diode clamps the output at -0.7 V and charges C to 14.3 V. From 270° onwards C remains charged at 14.3 V and the output follows the input with a +15 V offset.

• So far so good, your last figure shows that the output will stay at +15V for the first 180°, but it changes throughout the domain to 29.3 V, so can that first +15V be neglected? Because that's what I predicted too, but the source I'm studying from is beginning the output wave from 29.3 V – khaled014z Feb 26 at 3:28
• They are only giving you the steady state results after the initial "setup". I've shown both. "Can the first +15 V be neglected?" Maybe. Maybe not. It depends how your load will react and what you need it to do. – Transistor Feb 26 at 3:32

Assume negligible resistance for the Diode On resistance of say 1 Ohm per Amp and ESR of Cap of 1 Ohm per 100uF and is much smaller than RL.

Assume the impedance of the Cap is << RL at some frequency and uF

Then the Diode only turns on at the 1st half cycle and then only at just before sine peaks when diode restores charge drained slowly from RL.

Otherwise the Diode is OFF and the Cap has a stored DC voltage to pass AC thru to load.

Thus you have an "AC passthru with DC clamp" either positive or negative.

There is an offset due to the diode drop when ON. Better "Active Clamps" overcome this offset with a FET switch during peak zero crossing using dV/dt=0 for either positive or negative peak signals.

e.g. TV Video Hsync uses an Active Clamp to restore AC coupled video to DC = 0V = "Black Level" after sync pulse.

• So without the capacitor there is not 'AC passthrough' for the clipped voltage? – khaled014z Feb 26 at 3:05
• Correct. this converts an AC coupled signal to a DC restored to the diode drop near 0V tinyurl.com/y4xgnvad. But it is not clipped.since Vsource = 0 ohms here – Tony Stewart Sunnyskyguy EE75 Feb 26 at 3:07