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I have a digital 3.3V PWM signal that I want to send to a speaker, i.e.

  • amplify to higher voltage (e.g. 12V, but not sure)
  • and remove DC offset with a capacitor.

For the capacitor to work as intended, I think the amplification needs to be capable of sinking to ground.

After all I read, a push-pull amplifier should be doing the trick, but I don’t see how this can work without a negative supply rail. What are my alternatives?

schematic

simulate this circuit – Schematic created using CircuitLab

  • Since 12V > 3.3V, Q1 will essentially always be in saturation, thus in the configuration above, I’ll have a short circuit if Q2 is also in saturation.
  • If I exchange Q1 & Q2, then I won't have the voltage amplification any more, because as soon as C1 reaches 2.7V, the NPN transistor will be cut off. (And if it were not, soon after the PNP transistor would activate again.)
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    \$\begingroup\$ Indeed, your proposed circuit will not work. It will blow up one or both transistors as you basically connected two (Base-Emitter) diodes in series directly across the 12 V supply. What you need to do is stop trying to "design" a circuit without first looking at / studying existing circuits. What you want might be a "Class D amplifier" so use Google to find "class d circuit", look at some of the circuits. Try to understand how they work. Oh and be prepared that when this works, a 12 V PWM signal might damage the speaker. \$\endgroup\$ – Bimpelrekkie Feb 26 at 12:23
  • \$\begingroup\$ Without being so dramatic, add a 1k resistor at the base of each transistor. The current will be limited by C1 anyway, you won't blow anything up. You might need to make sure both transistor do not conduct at the same time, best would be to have 2 signal generator (simple to do with a MCU) with a dead time between the edges. \$\endgroup\$ – Damien Feb 26 at 12:27
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    \$\begingroup\$ @Damien The current will be limited by C1 anyway Explain to me how that works because I fail to understand your point. The base resistors will indeed "save" the transistors but still this circuit cannot work with a 3.3 V PWM signal as input. \$\endgroup\$ – Bimpelrekkie Feb 26 at 12:30
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    \$\begingroup\$ @Damien You're just repeating yourself, I want to hear an argument which explains why your statement is true. How does the capacitor limit the current. If the capacitor is 10 nF then indeed, the current would be too small to damage the speaker but also little wanted signal will come out. To get the wanted power output the capacitor needs a reasonably high value so it will have a low impedance at 30 kHz so the speaker can be damaged as the capacitor will behave as a short. \$\endgroup\$ – Bimpelrekkie Feb 26 at 12:38
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    \$\begingroup\$ ..the main difference.. Not really, the Maxim app-note discusses a completely different circuit. It is a commonly used circuit in DCDC converters and class D output stages. That "gate amplifier" is actually somewhat complex as it needs to drive between 0 and Vdd + some voltage. This is needed to get the upper NMOS fully conducting. You cannot just look at one example and think that you get it now. Being able to fully understand these designs takes a lot of practice, like years. \$\endgroup\$ – Bimpelrekkie Feb 26 at 12:46

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