1
\$\begingroup\$

I am trying to write a driver for an S70FL01GS chip, which is two stacked S25FL512S chips. I am successfully reading status register, SFDP register, RDID, etc. I am also able to toggle (and verify) the write enable bit in status reg using WREN and WRDI commands.

When I read/write/read, however, my read values are always the same. I am not sure if my write op is not going through, or if I am reading incorrectly. Here is my code for read() and write():

uint8_t transferSPI(uint8_t dataOut){ 
    int delay = 0xFFFF;
    PLIB_SPI_BufferClear(SPI_ID_2);
    while(delay-- && !PLIB_SPI_TransmitBufferIsEmpty(SPI_ID_2)); 
    if (!delay)
         return 0xFF;
    PLIB_SPI_BufferWrite(SPI_ID_2, dataOut);
    if (PLIB_SPI_ReceiverHasOverflowed(SPI_ID_2)){
         PLIB_SPI_BufferClear(SPI_ID_2);
         PLIB_SPI_ReceiverOverflowClear (SPI_ID_2);
         return 0xFF;
     }
     while(delay-- && !PLIB_SPI_ReceiverBufferIsFull(SPI_ID_2)); 
     if (!delay)
          return 0xFF;
     return PLIB_SPI_BufferRead(SPI_ID_2);
 }

 bool FLASH_Read(size_t addr, size_t len, uint8_t* data){
     int delay = 0x1FFF;
     int i;
     while(delay-- && (FLASH_RDSR() & 1)); 
     if (!delay)
         return false;
     FLASH_CS_SELECT();
     transferSPI(SPI_READ_CMD);
     transferSPI(addr >> 16);
     transferSPI(addr >> 8);
     transferSPI(addr);
     for (i = 0; i < len; i++)
         *data++ = transferSPI(0);
     FLASH_CS_DESELECT();
     return true;
 }

 bool FLASH_Write(size_t addr, size_t len, uint8_t* data){
     int i;
     int delay;
     delay = 0x1FFF;
     while(delay-- && (FLASH_RDSR() & 1)); 
     if (!delay)
         return false;
     delay = 0x1FFF;
     do { FLASH_WREN(); } while(delay-- && !(FLASH_RDSR() & 2));
     if (!delay)
         return false;  
     FLASH_CS_SELECT();
     transferSPI(SPI_PP_CMD);
     transferSPI(addr >> 16);
     transferSPI(addr >> 8);
     transferSPI(addr);
     for (i = 0; i < len; i++)
         transferSPI(data[i]);
     FLASH_CS_DESELECT();
     return true;
 }

I captured the signal using a logic analyzer, and took some screenshots of the read op, write op, and read SFDP reg op (which received the expected data correctly). Any help is greatly appreciated!

read op after write read op before write write op successful sfdp read

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Browse other questions tagged or ask your own question.