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Goals

I need to design resonant parallel circuit and simulate it with LTSpice so that it match with the design requirements correctly.


Requirements

  • Source Impedance \$R_s = 100\ \Omega\$
  • Load Impedance \$R_l = 1\ k\Omega\$
  • Resonant Frequency \$f_o = 100\ MHz\$
  • Bandwidth \$BW_{3dB} = 150\ kHz\$


Schematic

Resonator Circuit


Approach

  1. Find the value of the Quality Factor \$Q\$

    \$Q = \frac{f_o}{BW_{3dB}}\$

    \$Q = \frac{100\ MHz}{150\ kHz}\$

    \$\therefore Q = 666.\overline{6}\$

    \$\$

  2. Find the value of the Parallel Resistance \$R_p\$

    \$R_p = 100 // 1k\$

    \$R_p = \frac{100\ \cdot\ 1k}{100+1k}\$

    \$\therefore R_p = 90.\overline{90}\ \Omega\$

    \$\$

  3. Find the value of the Parallel Reactance \$X_p\$

    Consider the fact that \$Q = Q_p = Q_s\$

    \$Q_p = \frac{R_p}{X_p}\$

    \$X_p = \frac{R_p}{Q_p}\$

    \$X_p = \frac{90.\overline{90}}{666.\overline{6}}\$

    \$\therefore X_p = 0.1\overline{36}\ \Omega\$

    \$\$

  4. Find the value of the Inductance \$L\$

    \$X_p = 2 \pi f_o L\$

    \$L = \frac{X_p}{2 \pi f_o}\$

    \$L = \frac{0.1\overline{36}}{2 \pi\ \cdot\ 100 \times 10^6}\$

    \$\therefore L = 217.0294679\ pH\$

    \$\$

  5. Find the value of the Capacitance \$C\$

    \$X_p = \frac{1}{2 \pi f_o C}\$

    \$C = \frac{1}{2 \pi f_o X_p}\$

    \$C = \frac{1}{2 \pi\ \cdot\ 100 \times 10^6\ \cdot\ 0.1\overline{36}}\$

    \$\therefore C = 11.67136249\ nF\$

    \$\$


Frequency Response

Resonator Resonant Frequency


Bandwidth

Resonator Bandwidth


Insertion Loss

Insertion Loss is the ratio of power or voltage of the output with load and without the load. At the resonant frequency the reactance of the circuit is equal to zero, so it'll form a simple voltage divider.

\$IL = 20\ log_{10}{\left(\frac{V_{outWithLoad}}{V_{outWithoutLoad}} \right)}\$

\$IL = 20\ log_{10}{\left(\frac{\frac{R_l}{R_s+R_l}V_{in}}{V_{in}} \right)}\$

\$IL = 20\ log_{10}{\left(\frac{1k}{1.1k}\right)}\$

\$\therefore IL = -0.8278537032\ dB\$


Questions

  1. Why at resonant frequency I got \$-16.228\ dB\$ on the simulation graph instead of \$-0.827\ dB\$ which I calculated from Insertion Loss before?

  2. Why at both cutoff frequency of \$99.925\ MHz\$ and \$100.075\ MHz\$ from the simulation graph I got \$-16.35\ dB\$ instead of \$-3.827\ dB\$?

  3. If impedance load causes insertion loss, then what does impedance source causes loss at? How to calculate it? Is it the something that is missing with my calculation?

  4. Is there something wrong with my approach? I have also tried double precision settings on the LTSpice with .OPTIONS numdgt=7 and the results are still the same.

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  • \$\begingroup\$ The "Q" factor you are trying to achieve requires multiple cascaded filter sections. Be warned: this is non-trivial when calculating manually. However, there is software available on-line that will assist you. \$\endgroup\$ – Dwayne Reid Feb 26 at 21:05
  • \$\begingroup\$ As Dwayne said, there are lots of apps online to do this. Search for 'Impedance Matching Network Designer", without the quotes. \$\endgroup\$ – Digiproc Feb 26 at 21:16
  • \$\begingroup\$ @DwayneReid I've found a good one in here, it can design over 20th order. I understand that higher order means tight tolerances towards ideal. But, is there any other disadvantage besides of lower tolerance towards ideal? \$\endgroup\$ – Unknown123 Feb 26 at 21:52
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Inductors in LTSpice by default have non-zero series resistance.

If I explicitly set the inductor resistance in your circuit to zero (and zoom in the frequency range being measured), I see

enter image description here

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  • \$\begingroup\$ Unbelievable, just a very very tiny mistakes can ruin everything! I just have enough of this. sigh. \$\endgroup\$ – Unknown123 Feb 26 at 21:38
  • \$\begingroup\$ Would you mind to also answer my third question? "If impedance load causes insertion loss, then what does impedance source causes loss at? How to calculate it?" give me a link or answer it in comments it's alright, thank you. \$\endgroup\$ – Unknown123 Feb 26 at 21:39
  • \$\begingroup\$ @photon, do you concur with my answer? \$\endgroup\$ – Sunnyskyguy EE75 Feb 26 at 22:03
  • \$\begingroup\$ @SunnyskyguyEE75, I agree the filter as presented isn't realizable in discretes. I don't see where OP said they're trying to model a discrete filter. This could be a model of a transmission line filter, or a ceramic resonator or some other type of device. Or it could be how OP figures out their goals aren't reachable with discretes. \$\endgroup\$ – The Photon Feb 26 at 22:18
  • \$\begingroup\$ @Unknown123, now that you know how to get the simulator to model what you want, you can explore the effect of source and load loading on your own. \$\endgroup\$ – The Photon Feb 26 at 22:21
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Your filter Q is unrealizable with magnetic inductors. However with a precision large Helix antenna you can get a Q of 1000 @ 100MHz

Since magnetic inductors depend on the Length/diameter ratio per unit length ( e.g. 500 pH/mm) and resistance depends on the cross-sect. area/length ratio * resistivity to get ohms/mm for DCR resistance there is a limitation on the L/DCR Quality factor for inductors.

In order to achieve a high Q , the geometric must be a perfect helicoil with extremely tight tolerances at 100MHz. In practice Q=300 is a reasonable limit but you cannot make this if the length is < 1mm so these parts tend to be > 10nH.

4 turns 550 microhms 22nH enter image description here


This part has an inductance of 200 pH and DCR= 100 mΩ Q=5 @ 500MHz which is about 133 times too high resistance ( which is made with printed nichrome traces)

enter image description here

Your design has Xp=0.136 Ω Q=666 ∴ DCR or Rs=Xp/Q= 0.2 mΩ and the same is true for ESR on the cap.

Conclusion

Plan on changing your design specs. This is why IF filters were invented for FM.

Load impedance causes almost no insertion loss. From simple impedance divider.

Power Insertion Loss = \$10 log \frac{R_L}{R_S+R_L}= -0.4 dB \$ neglecting the Cap ESR and inductor DCR.

My Rule of Thumb

Due to the effects of DCR in the coil and ESR in the cap, for > 20MHz it more practical to choose SERIES RESONANT circuits than Parallel. The same is true for Xtals and other resonators. This requires a low impedance source which can be accomplished in many ways.

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  • \$\begingroup\$ Well, I have no plan at the moment in realizing it in real life. I'm just learning while simulating it. It's a new information for me. But surely your answer may help everyone in the future. \$\endgroup\$ – Unknown123 Feb 26 at 21:56
  • \$\begingroup\$ By the way my third question hasn't been answered, would you like to answer it? "If impedance load causes insertion loss, then what does impedance source causes loss at? How to calculate it?" \$\endgroup\$ – Unknown123 Feb 26 at 21:56
  • \$\begingroup\$ I answered that \$\endgroup\$ – Sunnyskyguy EE75 Feb 26 at 22:01
  • \$\begingroup\$ You are answering the loss because of load impedance isn't it? I'm asking for the loss because of source impedance \$\endgroup\$ – Unknown123 Feb 26 at 22:04
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    \$\begingroup\$ yes power loss is 0.4 dB and voltage loss is 0.8dB \$\endgroup\$ – Sunnyskyguy EE75 Feb 26 at 22:38

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