# 1-bit maximum selector (iterative design)

I'm trying to create a 1-bit maximum value selector with an iterative design that can solve larger problems. I understand that I go from the most significant bit (MSB) to the least significant (LSB), but am struggling with the design process as a whole. The following picture shows the original 2-bit maximum value selector I have created: (Two inputs, A and B, represented by a1, a0, b1, and b0 respectively. C, the output, is represented by c1 and c0. C's value is determined by which value is larger, A or B. So, for example, a1 is 1, a0 is 0, b1 is 0, and b0 is 1. A is larger than B, so c1 = 1 and c0 = 0.)

I understand that I can use an OR gate in order to determine if A and B are the same values or not, as well as outputting 3 things (If A or B are equal, A is greater, B is greater.) But I am unsure on how the 1-bit devices would communicate to another 1-bit device about the stage they are on, as well as how to determine which of the inputs is greater than the other. (Perhaps with a multiplexer?)

• Why not just use any number of optimized cascadable adders to compare the full width words and then use the result of the comparison to select the larger of the two inputs to send to the output? – crj11 Feb 27 at 3:37
• You have the basics of a priority encoder, who's output can be an index or arbitrary values. – Sparky256 Feb 27 at 4:08
• Thanks @crj11 for the advice, I have done what you have suggested and have come up with the correct answer. – JD D Feb 27 at 4:58