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I'm thinking about 1Mhz clock signal synchronised to external random pulses (eg. rising edge).

  1. Before pulse event clock can be running or stopped.
  2. After every pulse, it should run in same fixed phase relationship with a pulse to give low jitter relative timings.
  3. Clock will be used to drive multiple ADC conversions. Idea is to have precisely same sampling points relative to pulse with minimal jitter.
  4. Absolute timing values are not important they just need to be same after every new pulse.
  5. Jitter less than 1ns would be nice.
  6. Long term stability (>1 minute) is not very important.

What could be options? Maybe industry standard solution exist? MCU interrupt is not an option, because for example with 100Mhz MCU jitter cannot be less than 10ns and can also be worse for software reasons. And I whould not like to go to Ghz range MCU, MPU or FPGA. That whould be overkill for my application. Can RC oscillator be a choice? I thought about holding capacitor bypassed and releasing it after pulse so RC oscillator can continue from the same known state every time. But I worry, that it will not be accurate enougth, or can it? Is there some IC's that could be worth trying?

Edit: Best reprensentation is an oscilloscope. It triggers and samples waveform. On a good scope, with very low jitter triggering same input will give same picture. I'm doing same, there is trigger and signal (complex non periodic waveform). I want my samples to have as little noise as possible. At this moment I'm doing it with ISR, but MCU clock is not synchronised with trigger source, so I get noise because of jitter when sampling sloping signal. I can average, but then it reduces bandwidth. So I was thinking to do better.

<1ns jitter for 100 samples (clocks) after trigger would be goal. Clock must run 100 cycles after trigger. First clock edge can have delay maybe 1 to 3 clocks. Frequency is not important, as long as it is same after every trigger. Long term drift (minutes) is ok.

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  • \$\begingroup\$ A knowledgeable answer, that this cannot be achieved in a reasonable simple way will also be accepted as answer. \$\endgroup\$ – Vincent Mar 1 at 19:50
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    \$\begingroup\$ I get the general idea, but we need numbers. You say 10ns jitter is too much, so what level is "good enough"? How long must the clock run after each pulse, and how accurate must the frequency be during that time? How soon after the pulse must the first clock edge appear? \$\endgroup\$ – Dave Tweed Mar 1 at 19:59
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    \$\begingroup\$ Also, I detect some hint of an X-Y problem here. Describe exactly what it is you're trying to accomplish. Even with asynchronous sampling, it is possible to analyze or time-shift a properly band-limited signal with fractional-cycle resolution. \$\endgroup\$ – Dave Tweed Mar 1 at 20:04
  • \$\begingroup\$ A timing diagram would be immensely helpful \$\endgroup\$ – Scott Seidman Mar 2 at 15:26
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Maybe industry standard solution exist?

No, because nobody does it that way. As I said, there are DSP techniques for extracting information (such as trigger points) to subsample resolution even when using a continuous asynchronous sampling clock.

For example, suppose you want to know when the signal crosses zero, but none of your samples is exactly zero. But there's going to be a point at which one sample is negative and the next sample is positive. Obviously, the signal crossed zero somewhere in between those samples.

If you draw a straight line between them, it's simple algebra to find the exact time of the zero crossing. You can also use more complex forms of interpolation, but the principle remains the same.

And assuming that the signal is properly bandlimited in the first place, any set of samples, regardless of their phase, contains the same information. It's up to you to pick the analysis technique that extracts the features/parameters that are important to your application.

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  • \$\begingroup\$ Suppose I have first trigger after which I take multiple samples of signal. Then there is second trigger and multiple samples. How can I tell between second set of samples "time shifted" vs signal actually changed? By interpolation you mean to rebuild signal shape with higher resolution then try to match first with second in time domain and then it becomes possible to compare amplitudes? This is how it is done "correctly"? \$\endgroup\$ – Vincent Mar 2 at 17:10
  • \$\begingroup\$ Not higher resolution, just time-shifted (i.e., resampled). You can construct an all-pass FIR filter that shifts one of the signals by some fraction of a sample (determined by the analysis described above) so that their trigger points line up exactly, and then compare the samples. This is how a standard DSO displays waveforms. Or you could use something like a Fourier transform, which allows you to separate the effects of phase (time shift) from your comparison. \$\endgroup\$ – Dave Tweed Mar 2 at 17:17

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