I'm thinking about 1Mhz clock signal synchronised to external random pulses (eg. rising edge).
- Before pulse event clock can be running or stopped.
- After every pulse, it should run in same fixed phase relationship with a pulse to give low jitter relative timings.
- Clock will be used to drive multiple ADC conversions. Idea is to have precisely same sampling points relative to pulse with minimal jitter.
- Absolute timing values are not important they just need to be same after every new pulse.
- Jitter less than 1ns would be nice.
- Long term stability (>1 minute) is not very important.
What could be options? Maybe industry standard solution exist? MCU interrupt is not an option, because for example with 100Mhz MCU jitter cannot be less than 10ns and can also be worse for software reasons. And I whould not like to go to Ghz range MCU, MPU or FPGA. That whould be overkill for my application. Can RC oscillator be a choice? I thought about holding capacitor bypassed and releasing it after pulse so RC oscillator can continue from the same known state every time. But I worry, that it will not be accurate enougth, or can it? Is there some IC's that could be worth trying?
Edit: Best reprensentation is an oscilloscope. It triggers and samples waveform. On a good scope, with very low jitter triggering same input will give same picture. I'm doing same, there is trigger and signal (complex non periodic waveform). I want my samples to have as little noise as possible. At this moment I'm doing it with ISR, but MCU clock is not synchronised with trigger source, so I get noise because of jitter when sampling sloping signal. I can average, but then it reduces bandwidth. So I was thinking to do better.
<1ns jitter for 100 samples (clocks) after trigger would be goal. Clock must run 100 cycles after trigger. First clock edge can have delay maybe 1 to 3 clocks. Frequency is not important, as long as it is same after every trigger. Long term drift (minutes) is ok.