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I'm not sure about at which stage do the address computation take place at each of the versions of the risc-v?

I just wanted to make sure i got that right- Single-cycle risc-v: Branch target address computation happens at Execute stage multi-cycle risc-v: Branch target address computation happens at Decode stage Pipeline risc-v: Branch target address computation happens at Execute stage

Thank you!

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  • In single-cycle processors, everything is calculated during one cycle and there is no dividing into the stages. For example on the following image is the single-cycle MIPS processor from This book.

enter image description here

The branch address is the signal PCBranch.

  • In pipelined processors, however, every instruction executing is divided into five stages:
    Instruction Fetch
    Instruction Decode
    Execute (ALU)
    Memory
    Write Back

The complete pipelined MIPS is on the following image

enter image description here

The address is calculated in the Execute stage but taken in Memory stage.

  • I did not work with multi-cycle processors, but according to the book and the following image, the address is calculated in the Execute stage. The signals flowing during beq instruction is shown with dotted-line.

enter image description here

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  • \$\begingroup\$ First of all thank you! you are right about the stages at single-cycle, there are no stages... but I think that in risc it's a bit different than in mips (in out lecture notes it is stated that in multi-cycle the branch target address is computed at decode stage) but there's nothing written about pipeline or whether in single-cycle the branch comperator makes the branch decision in parallel to the address computation or after it... \$\endgroup\$ – E. Ginzburg Mar 2 '19 at 14:12
  • \$\begingroup\$ @E.Ginzburg It is all in the control unit. Your instruction is divided into bits, where usually first 6 bits define what this instruction should do. You can see in the pictures, that on the left side of the control unit there is 31:26 bits going into the control unit. And then the control unit decides how to set control signals. So maybe the decision about branch is made in the decode stage, since CU is placed in the decode stage. \$\endgroup\$ – litvinik Mar 2 '19 at 16:51
  • \$\begingroup\$ @E.Ginzburg I really suggest you to read the book I mentioned. It can be found [here]. (hron.fei.tuke.sk/~adam/cas/…) Chapter seven is all about constructing the single-cycle processor. By the way, MIPS is RISC and all processors are working in the almost same way, I believe. So understanding one will help you with others. It is greatly explained in this book and I suggest you spend at least an hour and I am sure you will find an answer to your question :) \$\endgroup\$ – litvinik Mar 2 '19 at 16:55

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