# Building a 6-inputs XOR gate with only 12 AND/OR gates

I would like to compute a 6-input XOR gate with only 12 AND/OR gates, any number of inverters can be used. I failed to find any optimization with the K-map and so far I can only decompose it with 13 gates. How can I find a solution, what method should I be using ?

What I got so far :

• This sounds like a homework question. Please show us all of your work, including your K-map solution that results in 13 gates. You should also provide a truth-table for your 6-input XOR as the definition of an XOR with more than two inputs is ambiguous. – Elliot Alderson Mar 3 at 19:03
• My K-map doesn't result in 13 gates, that's the problem, but I still figured it out with combining 2 3-input XOR as 2 1-input XOR (see circuit above). As you can see, the notion of a XOR gate is not the issue here, I just don't know what method should be used. – jaxmax Mar 3 at 19:29
• It appears obvious (but I could be wrong - this is your home work - so I'll leave it to you to prove it out) that the 1st layer of 8 AND gates can be replaced by 6 NAND gates (inverters are free, right). All you really want is to block a truth from getting through if any 2 of the 3 inputs are true. Hence 3 NAND gates. Then replace the 2nd layer with a pair of 6 input AND gates. But, as this is an exercise and not the real world - likely you need to show your work (i.e. break it down into a map, truth table or equation). – st2000 Mar 3 at 19:59
• Well, there are two possible definitions for a 6-input XOR gate function so, yes, it does kind of matter here. It sounds like your instructor provided you with the definition you are required to use, is that correct? – Elliot Alderson Mar 3 at 20:03
• I don't have any instructors so I don't know. It's just a question I've found without any further details. Would it be possible to do it with an "addition mod 2" definition ? – jaxmax Mar 3 at 20:41