I'm wondering how to optimize comparison a wide counter value with few defined values. Maybe it will be easier if I show it on example - let say there is a receiver that gets data in well defined format - 1004, 8-bit symbols are grouped in one frame. In every CLK cycle one 8-bit symbol appears on receiver input. The last four symbols in frame are sequence number, that helps the receiver to find boundaries of frames. So, useful data that should be forwarded to next module are 1000 symbols. But, these symbols are also grouped in 4 smaller subframes, 250 symbols each one. Subframes are aligned to bigger frame's boundary - 1st symbol of bigger frame is also first symbol of 1st subframe. I would like to filter out sequence symbols in big frame, forward encapsulated data to next module and set additional output signal that shows subframes' beginnings.
My fist idea was to build state machine that looks where are big frames boundaries. If it catches sync sequence few times, it goes to sync state. Then use 10-bit counter that counts every symbols. On counter values 0, 250, 500, 750 would be subframes' 1st symbols (that I can signalise to next module by additional output signal - call it StartOut), and on counter values 1000-1003 the next module should be disabled, to skip sync sequence. Unfortunately this solution is not so good - output signals Enable and StartOut are functions of 10 bits. There are some logic (including 10-bit comparators) that slows down output signals' maximum speed. It becomes more limited if big frame size increases, and 16-bit counter is needed.
Searching StackExchange I found this question: vhdl synthesis optimization: counters in statemachines. There is shown an idea how to reduce output signal dependency, and make it a function of only one 1-bit signal. But it works rather with counting to one value. Here is a problem of one counter and few values that should be compared with it.
Do you have any idea how to improve speed in comparison counter with few constant values?