I have the following verilog code that I came across and trying to find the sequence of evaluation. What value does 'A' have at the end of a cycle and after 5 cycles, when the value of A is 'x' at cycle 0.
always @ (posedge clk) A <= 1; A <= A+1; B <= A+1;
I understand that the evaluation of RHS is done on the posedge and the assignment happens at the end of the cycle. What value would A have after the assignment? Is it '1' or 'X'?
Also does adding the delay to the statements act as blocking for the following code?
always @ (posedge clk) begin #5 A<=1; #5 A<=A+1; B <=A+1; end