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I have to create a 4-bit ripple carry adder/subtractor. The circuit will have two 4-bit data inputs (A and B), a control line (Add/Sub), a 4-bit data outputs (S) and a carry out bit (Cout).

I have no idea where to get started. I know how to create a ripple adder but have no idea how I am supposed to create a 4-bit ripple carry adder/subtractor with the specified inputs, control line and specified outputs. Here is what I have so far:

fulladd:

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY fulladd IS
PORT ( Cin, x, y : IN STD_LOGIC ;
    s, Cout : OUT STD_LOGIC ) ;
END fulladd ;

ARCHITECTURE LogicFunc OF fulladd IS
BEGIN
s <= x XOR y XOR Cin ;
Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;
END LogicFunc ;

adder4:

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY adder4 IS
PORT (  Cin     : IN    STD_LOGIC ;
    X, Y    : IN    STD_LOGIC_VECTOR(3 DOWNTO 0) ;
    S   : OUT   STD_LOGIC_VECTOR(3 DOWNTO 0) ;
    Cout    : OUT   STD_LOGIC ) ;
END adder4 ;

ARCHITECTURE Structure OF adder4 IS
SIGNAL C : STD_LOGIC_VECTOR(1 TO 3) ;
COMPONENT fulladd
    PORT ( Cin, x, y    : IN STD_LOGIC ;
            s, Cout     : OUT STD_LOGIC ) ;
END COMPONENT; 
BEGIN
stage0: fulladd PORT MAP ( (Cin Xor X(0)), Y(0), Cin, S(0), C(1) ) ;
stage1: fulladd PORT MAP ( (Cin Xor X(1)), Y(1), C(1), S(1), C(2) ) ;
stage2: fulladd PORT MAP ( (Cin Xor X(2)), Y(2), C(2), S(2), C(3) ) ;
stage3: fulladd PORT MAP ( (Cin Xor X(3)), Y(3), C(3), S(3), Cout ) ;
END Structure ;
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  • 1
    \$\begingroup\$ Welcome to EE.SE! This appears to be a homework question. As such, you need to show us your work so far, and explain which part of the question you're having trouble with. For future reference: Homework questions on EE.SE enjoy/suffer a special treatment. We don't provide complete answers, we only provide hints or Socratic questions, and only when you have demonstrated sufficient effort of your own. Otherwise, we would be doing you a disservice, and getting swamped by homework questions at the same time. See also here. \$\endgroup\$ – Dave Tweed Mar 5 at 12:37
  • \$\begingroup\$ @JackFlower now think about how you would subtract two binary numbers on paper. \$\endgroup\$ – Kevin Kruse Mar 5 at 16:28
  • \$\begingroup\$ @KevinKruse So A-B = (A + B bar), so when I need to subtract i need to take the complement of B and add it. But how would I create that implementation in Vhdl. \$\endgroup\$ – Jack Flower Mar 5 at 16:43
  • \$\begingroup\$ @JackFlower have you learned Two's Complement yet? After negating B you will also need to add 1. Negating B if (and only if) you're asked to perform subtraction should be straightforward. \$\endgroup\$ – Kevin Kruse Mar 5 at 17:44
  • \$\begingroup\$ But how would I know when to substract? When Cin is 1? \$\endgroup\$ – Jack Flower Mar 5 at 17:48
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Once you have a Ripple-Carry Adder (as you had in your Question), you can create a Ripple-Carry Adder-Subtractor with a little extra logic.

Note: The Answer here is given without a concrete "this is the VHDL code" solution. Homework Questions on EE.SE (provided a reasonable effort is put into the Question) are met with Socratic questions and general tips to guide the student to the solution.

Your adder implements the following operation (in this revision of your adder.):

$$ Sum = A + B $$

You're tasked with adding a control line (Add/Sub) to make your adder perform both addition and subtraction. When commanded to subtract, the operation should be:

$$ Difference = A - B = A + (-B)$$

Now that you've transformed your subtraction operation back into an addition operation, we just need to find \$-B\$. From Two's Complement we know:

$$ -B = \bar{B} + 1 $$

Let's establish a convention. When our input add_sub is 1, we'll do subtraction. When add_sub is 0, we'll do addition. So when add_sub is 1, we need to:

  • Invert B
  • Add 1

Thus we have:

B <= B_in XOR add_sub;

Finally, adding 1. Hey, isn't that what would happen if Cin is 1? So make Cin = 1 when add_sub = 1...

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