Error with reference to scalar wire 'reset' is not a legal reg or variable lvalue

Question

I'm getting an error in Verilog with an input parameter it's not recognized as a legal reg or a variable lvalue. I had the same problem with the output in the module however it was fixed by labeling it as a reg. It's the only error in my code and it occurs only at the input reset variable in the always block.

module lasersystem(input clk, input reset, output reg click
     );

reg [1:0] next_state = 2'b00;
localparam off = 2'b00, start = 2'b01, on = 2'b10;
reg [32:0] counter;


always @ (clk)
begin
case (next_state)

off: if (clk == 0) begin
        next_state = off;
        reset = 1;
        counter = 32'd0;
        click = 0;
        end

      else if (clk == 1) begin
        next_state = start;
        reset = 1;
        counter = 32'd0;
        click = 0;
        end

start: if (clk == 1) begin
          reset = 0;
          click = 0;
          counter = 32'd0;
          next_state = on;
        end

         else begin
          next_state = on;
          reset = 0;
          counter = 32'd0;
          click = 0;
         end

on: if (clk == 1) begin
        reset = 0;
        click = 1;
        if (counter == 32'd249999999) begin
            next_state = off;
        end
        else if (counter != 32'd249999999)
            next_state = on;
    end

default: next_state = off;
endcase
end

always @ (posedge clk) begin
case (reset)
    1: if (next_state == off) while (counter > 32'd0 && counter <     32'd250000000) counter = counter - 32'd1;

    0: if (next_state == on) while (counter > 32'd0 && counter < 32'd250000000) counter = counter + 32'd1;

default: counter = 32'd0;
endcase
end     
endmodule

Why does this happen?

Answer 1

If your state machine needs to set reset, then you need to specify it as an output reg reset of your module. Outputs default to nets unless you add a data type like reg. Then they are treated like variable that can be procedurally assigned from your `always1 block.