As per my understanding the ARM M4 core registers such as NVIC registers can be accessed only when the software is in privileged mode, that means it should be running in handler mode if I am correct. I am wondering how does the CMSIS functions are able to access the core registers while running in thread mode. As per my understanding during the normal program execution time the core will be in thread mode and it should not be possible to write the core registers as it is only available in privileged mode. Please correct me if my understandings are wrong and help me to clarify this doubt.


1 Answer 1


This question seems to arise from a confusion between Thread vs Handler modes and Privileged vs Unprivileged modes.

To quote the Cortex M4 Technical Reference Manual:

The processor enters Thread mode on Reset, or as a result of an exception return. Privileged and Unprivileged code can run in Thread mode.

The processor enters Handler mode as a result of an exception. All code is privileged in Handler mode.

Necessarily speaking, the processor would need to start out in privileged mode so that key setup configuration can be accomplished.

An operating system or stack sophisticated enough to make use of an unprivileged mode would then need to explicitly activate it to impose those restrictions on "user" code.

If no part of the code on a system manipulates privilege levels, then whole thing is running in privileged mode, just as it might on a simpler processor not offering a distinction.


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