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I'm new to modelsim and Verilog and I have got an error in it:

#         Region: /seqdectorTB
# Error loading design

1.3.v:

module myseqdetector(x,clk,reset,y);
  input x,clk,reset;
  output reg y;
  reg[2:0] ps,ns;
  always@(posedge clk)
  begin
    if(reset)begin
      ps<=2'b00;
    end
    else begin
     ps<=ns;
    end
  end
  always@(ps or x)
  begin
    case(ps)
      3'b000 : ns = x? 3'b000 : 3'b001;
      3'b001 : ns = x? 3'b010 : 3'b001;
      3'b010 : ns = x? 3'b000 : 3'b011;
      3'b011 : ns = x? 3'b100 : 3'b001;
      3'b100 : ns = x? 3'b000 : 3'b101;
      3'b101 : ns = x? 3'b100 : 3'b110;
      3'b110 : ns = x? 3'b010 : 3'b001;
    endcase
  end
  always@(ps or x)
  begin
    case(ps)
      3'b000 :y = 1'b0;
      3'b001 :y = 1'b0;
      3'b010 :y = 1'b0;
      3'b011 :y = 1'b0;
      3'b100 :y = 1'b0;
      3'b101 :y = 1'b0;
      3'b110 :y = 1'b1;
    endcase
  end
endmodule




my testbench 1.3tb.v:
module seqdectorTB();
  parameter clkperiod=100;
  reg x,clk,reset;
  wire y;
  myseqdetector(x,clk,reset,y);

  initial begin
   clk = 0;
   forever #100 clk = ~clk;
  end
  initial begin
    reset=1;
    #101 x=1;
    #201 x=0;
    #301 x=1;
    #401 x=0;
    #501 x=1;
    #601 x=1;
    #701 x=0;
    #801 x=1;
    #901 x=0;
    #1010 x=1;
    #1101 x=0;
  end
endmodule

thanks all

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You have syntax errors in your testbench 1.3tb.v file that you should have seen before the "Error loading design" message. Please correct them.

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