Ripple in full wave rectifier

Question

I've searched the forums but have not found what I'm looking for. The problem at hand is that I have no idea how to successfully calculate the ripple over the load in this schematic:

^{simulate this circuit – Schematic created using CircuitLab}

I know that Vripple = i / 2fC where i is the current over the load. But this is the ripple over/in R1. Not over the load. So the question is, how do I calculate the voltage ripple on Rload? I thought some kind of voltage divider. When I attempt it I compare the values to the simulated values I get in Multisim. Not even close which makes me think that I have absolutely no clue where to start.

Some values that might be useful: Vpeak = 16.97 V, Voltage drop of 0.7 over each diode, zener voltage is 10 V. Everything else is given in the circuit above. Zener current in this circuit is (15.57-10)/180 = 31 mA

Thanks for any advice and pointers.

EDIT: Is this it? I still have no idea how to calculate ripple though. The voltage over the capacitor will not change so it will always be 15.57 volts. More tips? I honestly have no idea what to do next. In my head everything in this value in this circuit changes based on the load which makes this so much harder to calculate.

^{simulate this circuit}

Answer 1

A rectifier is non-linear, which means that a Thevenin model must be used very carefully. Ripple in rectifiers is generally carried out as follows:

1) Assume that, at peak input voltage, the filter capacitor is charged to the peak value. This is a good first-order assumption, since the dynamic resistance of diodes is small for large difference voltages.

2) Assume that, once the peak has passed, the rectifier will not conduct until the next rectified peak. In the case of a full-wave bridge and 50 Hz, this is 10 msec.

3) Between 1 and 2 there is no current into the filter cap, and it provides all of the current to the load. Using the load characteristics, you can calculate the droop on the filter cap over the designated time period. This is the ripple voltage.

Answer 2

A zener diode acts like a voltage source in series with a resistor. So you look up the effective resistance (it's called "dynamic resistance" in the data sheet) and you treat the diode as a Thevenin-equivalent voltage source with that dynamic resistance.

Or, you just use a 3-terminal adjustable regulator :).

Answer 3

First calculate the ripple at the capacitor. Assume it is only charged at the peaks of the mains. So you will get a 100Hz sawtooth with amplitude:

Vrc = \$\frac{0.01 I_L}{C}\$

The current to the zener and load (from the filter capacitor) will be more-or-less constant at about (15.57V-10V)/180 = 31mA. Well, it would be if the load wasn't so low. If the peak output voltage is 15.57 then the peak voltage across the zener will be 100/280 times 15.57 or about 5.6V. So we can ignore the zener and do a simple calculation.

Now the load current is 15.57/280 = 55mA and the ripple at the capacitor is around 5.5Vp-p (actually a bit less since the ripple is so high, call it 47mA and 5Vp-p ripple).

The average output voltage is about 4.7V and the ripple at the output resistor is about 1.8Vp-p. Turns out if you do a simulation this is bit pessimistic because the ripple is so large so charging takes place over more of the cycle. Average is about 5.05V. Anyway, I doubt this is what you want.

For such a low load resistance (100mA at 10V) you'll want a much larger filter capacitor and a lower drop regulator.

Answer 4

Calculate peak voltage: Vpk = Vrms * SQRT(2) = 12 * SQRT(2) = 16.97V

Peak rectified voltage:

16.97 - 2 * 0.7 = 15.57V (voltage of fully charged capacitor)

Calculate load current (assuming zener is in breakdown): I = Vz / R = 10 / 100 = 0.1A

Zener reverse breakdown current = 5mA

Total required current thru R1 = 0.1 + 0.005 = 0.105A

Calculate required value of R1:

Voltage drop = 15.57 - 10 = 5.57V R = V / I = 5.57 / 0.105 = 53 ohms

As can be seen, the actual value of R1 (180R) is much higher than the required value (53R). Consequently, the zener diode will not enter reverse breakdown. R1 and Rload will therefore form a simple potential divider.

Maximum voltage across Rload = (15.57 * 100) / (180 + 100) = 5.56V

As can be seen, Rload is not being supplied the expected zener voltage.

To calculate the ripple voltage, R1 + Rload are the series load.

load current = 15.57 / (180 + 100) = 0.056A

Ripple = I / 2fC = 0.056 / 2 * 50 * 100 * 10^-6 = 5.6V

... however, this "ripple" is now a significant component of the rectified voltage and the approximation of I / 2fC may not be correct.

Answer 5

I still have no idea how to calculate ripple though.

It's a little more complicated than you think.

Design Specs

Input: 12 Vrms, 50 Hz at rated load = 17 Vp
Output: 10V @ 100 mA
Vmin: 10V+3V=13V unregulated for LM317 @100mA

Realize there are many reasons why this design is obsolete for LV regulators.

1. poor efficiency
2. high Input-to-output differential voltage = 3V
3. Huge Caps needed for low ripple V
4. High current crest factor resulting Iavg/Ipk % = low ripple %V

5. High diode losses due to (4.) above 1N4xxx = 1V @ 1 Apk

   V rect= 17-2V= 15Vp full wave rectified.

LM317 input drop 3V min.

Max ripple voltage = 2V = dV
%dV/V = 2/15 = 13.3% = 1/7.5
Ipk = Idc + Idc*V/dV = (1+7.5) * 100mA .... = 850 mA = Ic during charge peak, -100 mA during discharge

dt is not the 10ms interval but the time to pulse cap from sag voltage to peak voltage just before the sine peak then sags after sine peak voltage.

Choose dt= 20% of 10 ms interval = 2ms triangular pulse __|______|______

from Ic=C*dV/dt , C = Ic dt/dV = 850mA * 2ms / 2V = 850 uF

Since the current is triangular and the average of a triangle is roughly 1/3 peak the capacitance is proportional to current pulse , therefore C = 1/3 * 850uF = 283 uF

DVT capture (Design Validation Test by simulation)

Now your job is to compare the Design Specs with test results and compare. Then decide where the discrepancies occur and adjust the design specs. or results to meet 100mA load or use a better LDO regulator !!!

advanced

NEXT learn how to redesign this using a higher frequency (50kHz to 3 MHz) with a small inductor , smaller capacitor and a push-pull FET driver with feedback using a Vref diode to regulate error Voltage.