I am looking into the best practices for EEPROM and Flash memory testing. We are talking about end of line product testing by an ATE. The goal is to identify defect chip before writing memory content.

I have some trouble identifying what tests should be done and what failure mode it would target. RAM tests usually are more documented, but I am unsure if an EEPROM/Flash may fail the same way as a RAM.

For example, I noticed in the past that one EEPROM that was tested by writing all FF then all 00 had an undetected failure that corrupted a single byte. I know for a RAM chip that if the bus address is defect, we could see that behaviour. My questions : Would it be true for EEPROM and/or Flash?

I believe that doing these test should cover most case, but I can't tell if I might miss a significant type of failure :

  • Write all FF and read back
  • Write all 00 and read back
  • write all 55 and read back
  • Write all AA and read back
  • Write random sequence and read back

I would appreciate any good reference that treat the subject (in a concise manner :) )

EDIT : Since I got few close vote, I feel like I need to clarify my toughts. I am looking for information with this level of details and hopefully, some dos and don't from experienced manufacturing expert.

Thank you

  • \$\begingroup\$ Don't you want to make sure that the memory is non-volatile, that it retains its contents when the power is turned off? How long do you want the contents to be retained? Seconds? Years? \$\endgroup\$ – Elliot Alderson Mar 8 '19 at 17:41
  • \$\begingroup\$ Good point. Data retention should be ~20 years. But in the context of end of line testing, only seconds is an option. We'll have to rely on the manufacturer test and in house aging test (made on few samples). \$\endgroup\$ – Pier-Yves Lessard Mar 8 '19 at 17:54
  • \$\begingroup\$ Why the close vote? Seems like a legitimate questions. \$\endgroup\$ – Pier-Yves Lessard Mar 8 '19 at 20:27
  • \$\begingroup\$ This is a very broad topic, and doing it right requires knowledge of the chip's architecture. The fact that you asked for a "good reference" but specifically wanted one that is "concise" shows that you also know this is a broad subject. The question is just not a good fit for this site. \$\endgroup\$ – Elliot Alderson Mar 8 '19 at 21:50
  • \$\begingroup\$ Indded can be a broad subject. Subject can be anrrowed by keeping in mind end of line ATE testing. I believe PCB manufacturing experience is what is needed to answer. I still have faith that someone out there has good knowledge to share on the subject ;) \$\endgroup\$ – Pier-Yves Lessard Mar 8 '19 at 21:59

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