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I am writing a code in Verilog(FPGA) which works with the input clock frequency of 128khz, for my assignment my Ip core should be parameterized to work with clock frequencies from 128kHz to 100MHz. in order to do so, I should build a frequency divider circuit to create a clock enable signal for my servo controller. The frequency divider is used to reduce the incoming clock rate to a fixed value. could anyone guide me on how to build the frequency divider pls?

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closed as too broad by Eugene Sh., Elliot Alderson, Chris Stratton, Edgar Brown, laptop2d Mar 9 at 23:07

Please edit the question to limit it to a specific problem with enough detail to identify an adequate answer. Avoid asking multiple distinct questions at once. See the How to Ask page for help clarifying this question. If this question can be reworded to fit the rules in the help center, please edit the question.

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    \$\begingroup\$ You shouldn't be re-generating clocks in an FPGA fabric. They are unreliable and have skew and routing issues. If you truly need a clock, use the hardware PLLs and clock dividers present on the FPGA. I doubt you actually need a second clock in your case though. You probably just need a a clock enable that fires every N clock cycles to trigger events to happen, but only use it as a trigger. Do not clock anything off the clock enable. Still clock things off your main clock, and still clock your clock-enable pulses of the main clock. \$\endgroup\$ – DKNguyen Mar 8 at 19:14
  • \$\begingroup\$ Also, note that keywords like "posedge", "negedge", "rising_edge", and "falling_edge" in Verilog and VHDL are interpreted as clock signals by the synthesis software which means they are all given their own dedicated special clock routing network on the FPGA. These are there to run everywhere efficiently and prevent clock skew. That's why you don't want to re-generate clocks in FPGA fabric. You want to use these networks but you also don't want to waste them on pointless clock signals or things that are not clock signals (like asynchronous resets). \$\endgroup\$ – DKNguyen Mar 8 at 20:08
  • \$\begingroup\$ @Toor put this up as an answer I would vote for it. \$\endgroup\$ – RoyC Mar 9 at 12:36
  • \$\begingroup\$ Is it really? Okay...I guess. Doesn't seem like an answer to me as much as saying the OP is going about things the wrong way. \$\endgroup\$ – DKNguyen Mar 9 at 17:11
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You shouldn't be re-generating clocks in FPGA fabric. They are unreliable and have skew and routing issues. If you truly need a clock, use the hardware PLLs and clock dividers present on the FPGA. I doubt you actually need a second clock in your case though. You probably just need a a clock enable that fires every N clock cycles to trigger events to happen, but only use it as a trigger. Do not clock anything off the clock enable. Still clock things off your main clock, and still clock your clock-enable generator off the main clock.

Also, note that keywords like "posedge", "negedge", "rising_edge", and "falling_edge" in Verilog and VHDL are interpreted as clock signals by the synthesis software which means they are all given their own dedicated special clock routing network on the FPGA. These are there to run everywhere efficiently and prevent clock skew. That's why you don't want to re-generate clocks in FPGA fabric. You want to use these networks but you also don't want to waste them on pointless clock signals or things that are not clock signals (like asynchronous resets).

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