As you know, semiconductor technology is going to reach 7nm lithographic precision soon. Which means that the smallest segment length on a semiconductor die can be as short as 7nm. After making some calculations, I wondered how can someone dope such a small silicon block uniformly.

Density of silicon is \$2.328 \;\text{g}/\text{cm}^3\$.
Number of atoms in silicon is \$2.144217404 \times 10^{22} \;\text{atoms}/\text{g}\$.

Then we have number of atoms in unit volume as
\$(2.328 \;\text{g}/\text{cm}^3) * (2.144217404 \times 10^{22} \;\text{atoms}/\text{g}) ≈ 5 \times 10^{22} \;\text{atoms}/\text{cm}^3\$.

I read some papers online and deduced that a typical doping density is
\$10^{18} \;\text{doping-atoms}/\text{cm}^3\$. Which means that, the doping ratio is about \$50000\$ silicon atoms per each doping material atom.

Now, consider a \$7nm \times 7nm \times 7nm\$ cubic silicon block and we wish to dope it with atoms of some other material. Van Der Vaals radius of silicon atom is \$219pm\$ (found this on Google). After doing some elementary geometry calculation, we can find that \$4082\$ atoms can fit in this block.

We need
\$(4082 \;\text{silicon-atoms}) / (50000 \dfrac{\;\text{silicon-atoms}}{\text{doping-atoms}}) = 0.08164 \;\text{doping-atoms}\$
to dope this tiny 7nm x 7nm x 7nm cubic silicon block, which is less than 1. Which means a tiny block like this have a 8% change of receiving a single atom from the doping material. Which means there is a 92% change that the tiny block will remain pure silicon!

Seriously, what?!

I don't understand this and I have some questions on this.

  1. What happens if a supposedly P-type or N-type substrate (e.g.; emitter of a BJT or channel of a MOSFET) remains purely silicon?
  2. What happens if the block was lucky and it received a single atom of a doping material. Does it matter the location of that atom? What if the atom stays in the farthest corner of of the block?
  3. What happens if the block was super luck and it received more than 1 doping atoms?

In a chip which will contain more than 1 thousand transistors, occurrence of these kind of situations are statistically inevitable. How do they dope very small semiconductor materials? How do they overcome problems like this?

  • \$\begingroup\$ Taiwan Semiconductor Manufacturing Company (TSMC) is expected to kick off volume production of chips built using an enhanced 7nm with EUV node at the end of March and 5mm and end of Q2. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Mar 9 at 17:46
  • 3
    \$\begingroup\$ There is a conceptual error on your part. A 7um feature size does not imply a 7um cube, it is just the minimum 2-D resolution of the technology. It usually implies a minimum gate length of 14um and a width of >28um. Doping depth is not that clearly defined. \$\endgroup\$ – Edgar Brown Mar 9 at 17:47
  • \$\begingroup\$ @EdgarBrown, if you expand on that just a bit, it's worth posting as an answer. \$\endgroup\$ – The Photon Mar 9 at 17:52
  • \$\begingroup\$ Did the "some papers" you read apply specifically to process technologies in this range? I wouldn't apply knowledge about processes with larger feature sizes to a 7nm or 14nm process. \$\endgroup\$ – Elliot Alderson Mar 9 at 18:18
  • \$\begingroup\$ @EdgarBrown Of course those are nm and not um. And certainly not mm as Sunnyskyguy said. \$\endgroup\$ – Elliot Alderson Mar 9 at 19:06

The presence of dopants does not limit itself to just the vicinity of those dopants. Its job is to add a discrete energy level that either gives an extra electron to the conduction band (donor) or accepts an electron from the valence band (acceptor) resulting in an extra hole. That extra electron or hole is free to move around, even if there aren't any dopants nearby. So not having any dopants in a \$7x7x7 nm^3\$ cube is unlikely to be an issue.

Furthermore, a "smallest feature size of \$7nm\$" usually points to the minimum channel length of a transistor. Other structures may still require larger sizes.


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