The second layout is better than the first because this will cancel the unwanted induced voltage in the transistor. I don't understand how this will happen, I am trying to figure this out using the right-hand rule but I always fail. Please, someone, explain this in details and how to figure out exactly the polarity of the induced voltage in this case.
It seems that the author is suggesting that a PCB layout with built-in "twisted-pair" layout of the traces will result in lower EM pickup by the circuit board itself.
Figure 1. Untwisted and twisted PCB layout.
Shielded pair twisted pair cables reduce interference by nature of the twisting. Each twist of the cable picks up the EM interference in the opposite polarity to its neighbour with the result that the sum of all the interference tends towards zero due to cancellation.
To see how this happens, think of an external magnetic field noise source orientated directly out of the page (for example). Point your right hand thumb towards you so it points in the same direction as the magnetic field. Now curl your right hand fingers naturally - they'll circle anticlockwise. Trace around the two loops in the Figure above anticlockwise - notice how current induced in this way will be coming out of pin 1 (into pin 2) in the left loop, but out of pin 2 (into pin 1) in the right loop. The two loops mean stray magnetic fields (which direction they point) will induce noise currents that cancel each other out.
With the PCB layout suggested I would imagine that the crossover point should be set between the end of the infeed cable and the transistor such that the areas of the two opposing loops created are equal. Don't forget that the parallel pins of the connector will probably need to be considered as part of the first loop if one is going to this level of interference reduction.