I'm working on a digital circuit using discrete components to drive a 640x480 VGA display in a 80x30 text mode.
For a 640x480 display, the pixel clock is 25.175MHz, which has a period around 40ns. I don't understand how I'm supposed to be able provide a new pixel to the display this often.
The basic architecture for my circuit is as follows:
Binary counter for horizontal pixels counts up at 25.175MHz to 800 (640 visible pixels + 160 for front porch, sync, back porch). At 800, increment vertical line counter (and reset at 525 lines)
Using horizontal and vertical position, derive the x,y coordinate of current character.
Using x,y coordinate of character, index into video memory to retrieve ASCII character.
Use ASCII character to index in character ROM to obtain bit pattern for character
Use parallel to serial shift register to convert 8 pixel line of character to individual bits at pixel clock frequency
If you follow the chain, it goes: Counter -> RAM -> ROM -> Parallel to Serial Shift Register
Using the fastest components I can find, the propagation delays and access time add up to around 15ns + 20ns + 70ns + 15ns = 120ns, much greater than the 40ns period for 25MHz.
At even higher resolutions and refresh rates, you can have pixel clocks well above 100MHz which will be a 10ns period.
How is it possible to provide new pixels to the display every 10ns when just the access time for RAM/ROM are already well above it, not even considering all the other signals in your system?