Consider a bundle of wires carrying binary data and the worst case (or almost-worst case) scenario of them switching all at the same time. The wires with their partial mutual inductances would be aiding one another.

It can be found that if the currents are the same, then the magnetic fields are the same and if the currents have the same direction, these are aiding inductors.

enter image description here The loops are very independent, each wire forming its own LC circuit with some conceptual capacitance on the other end of the wire. Simulating this with 5 mutual inductances (expressed with coupling coefficients) in LTspice or PSpice yields a ringing peak of about 1.4 V instead of about 1.07 V with no mutual inductance.

From the simulations, no more than 1.4 V of peaking can be obtained maybe because they weren't intended for such a large number of mutual inductances. PSpice at least supports a maximum of 6 mutual terms.

However, it can also be found that, considering the mutual inductances, there is a very large matrix of the form:

enter image description here

Then, wouldn't all the mutual inductances add up to the self inductance to yield a very large ringing peak for every wire in the bundle?

  • \$\begingroup\$ Vi is actually Vi(t) so they signals would have to synchronous to add up to a peak value. \$\endgroup\$ – Sunnyskyguy EE75 Mar 10 at 1:22
  • \$\begingroup\$ For common parallel currents, ground bounce at the drivers could be an issue, Series resistors of 22 to 50 ohms dampen a lot of problems, yet have minor effects on rise/fall times. \$\endgroup\$ – Sparky256 Mar 10 at 2:04
  • \$\begingroup\$ This occurrence of massive currents, from VDD or into Ground, is why FET GATE power-drivers are a valuable interface between MCUs and FETs. \$\endgroup\$ – analogsystemsrf Mar 10 at 2:05

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Browse other questions tagged or ask your own question.