EDIT: I copied over the latch from another larger model that had Vdd defined, but missed it when copying over the design. However, after adding in Vdd, I still run into this confusing issue where the R seems to trigger Q and not S.
I used these 180nm mosfets to build this SR latch:
I used the nmos4 and pmos4 and added a spice directive with the models. I sized the nmos as L = .18um and W = .5u and the PMOS as L= .18u and W=1u (to get more symmetrical rise fall time, though Im not sure by what factor exactly I would need to scale the width):
However, even though I followed a regular schematic for an SR latch it does not work. When the S and R are triggered it seems that R triggers Q and not S. Then again, not all the parameters are recognized by ltspice and Im not sure how to get around that other than by using another transistor. Is there a way to make this current design work? Also, any chance someone could let me know if the warnings I am seeing are a clear need to fix a particular thing in the circuit?