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EDIT: I copied over the latch from another larger model that had Vdd defined, but missed it when copying over the design. However, after adding in Vdd, I still run into this confusing issue where the R seems to trigger Q and not S.

I used these 180nm mosfets to build this SR latch: enter image description here

I used the nmos4 and pmos4 and added a spice directive with the models. I sized the nmos as L = .18um and W = .5u and the PMOS as L= .18u and W=1u (to get more symmetrical rise fall time, though Im not sure by what factor exactly I would need to scale the width):

enter image description here

However, even though I followed a regular schematic for an SR latch it does not work. When the S and R are triggered it seems that R triggers Q and not S. Then again, not all the parameters are recognized by ltspice and Im not sure how to get around that other than by using another transistor. Is there a way to make this current design work? Also, any chance someone could let me know if the warnings I am seeing are a clear need to fix a particular thing in the circuit?

enter image description here [enter image description here

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    \$\begingroup\$ Look at the top CMOS stack, when S=1, Q=0. Is that what you desire? \$\endgroup\$
    – sstobbe
    Mar 10, 2019 at 19:27

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I don’t see a power source providing Vdd in your schematic. How would you expect that to work?

The spikes you see are just capacitive coupling.

Also, you mislabeled your nodes. Q and Qb are reversed.

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  • \$\begingroup\$ yes that is true. Thanks for pointing that out. I forgot to add in Vdd. It had been defined in the other segment of the circuit I did not include in this particular schematic \$\endgroup\$
    – user P520
    Mar 10, 2019 at 18:11

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