I do not understand the cause of this spike which can be observed in an RTL inverter (but also in a CMOS inverter). In the following image it is the peak at 10 mS (I have considered as input a signal which starts at 0V and begins VCC at 10mS).

enter image description here

I have been told that it is due to the parasitic capacitance between collector (output) and base (input), since at the high frequency of the vertical transition of the input signal it becomes a short circuit and therefore the output follows the input (which is now high) instead of going down. But, if the reason is this, why the output signal is higher than input (and not simply equal to it)?


Because that's how capacitors work — they resist a change in voltage across there terminals, until a current flows to add or remove some charge.

In this case, you have a sudden positive step on the base of the transistor. The B-C capacitance couples this step to the collector terminal. In order to reach equilibrium again, current must flow out of the collector terminal, and the only place it can go before the C-E conduction starts is through the load resistor R2. This forces the voltage on its lower terminal to briefly rise ABOVE the supply voltage on the other terminal.


Dave has given you the short-hand version and it's exactly right. I'll elaborate a little more about it.

Let's first look at the basic Ebers-Moll model (in the older literature, called the \$EM_1\$ model) and then follow it up with the modifications that were added in the next version (the \$EM_2\$ model) of the BJT, which adds a \$1^\text{st}\$ order modeling of the charge storage effects:


simulate this circuit – Schematic created using CircuitLab

The \$EM_1\$ model, shown above-left, is actually one of three equivalent models; the one called the hybrid-\$\pi\$ model. If you want to see all three equivalent models, see my writing here: EM1, transport, injection, and hybrid-\$\pi\$.

The \$EM_2\$ model, shown above-right, provides a little more accuracy with the DC modeling by adding in the Ohmic resistors indicated on the right plus a \$1^\text{st}\$ order AC approximation for the charge storage in the BJT. The AC bits are represented by \$C_\text{jC}\$ and \$C_\text{jE}\$ and are the "parasitic capacitances" you were told about.

Now, in your schematic you've provided a long time (\$10\:\text{ms}\$) such that these capacitors have fully charged up before the transition takes place at \$t=10\:\text{ms}\$. So \$C_\text{jC}\approx 12\:\text{V}\$ and \$C_\text{jE}\approx 0\:\text{V}\$ just before the transition takes place. (For small signal BJTs, you can assume that \$r_\text{b'}\approx 10\:\Omega\$, \$r_\text{c'}\approx \frac12\:\Omega\$, and \$r_\text{e'}\approx \frac12\:\Omega\$.)

When you yank upward on the base, via \$R_1=1\:\text{k}\Omega\$, this rapidly pulls upward on the bottom of \$C_\text{jC}\$ (that end of which was approximately at ground level a moment beforehand.) While it's true that \$C_\text{jE}\$ needs to charge upward via \$R_1+r_\text{b'}+r_\text{e'}\$ in order to allow the bottom of \$C_\text{jC}\$ to move upward, this occurs quite quickly as the total effective resistance is still only about the value of \$R_1\$ (and \$C_\text{jE}\$ is quite small, on the order of perhaps of a few tens of pF or so.)

Meanwhile, though, as the bottom of \$C_\text{jC}\$ rises pretty rapidly upward, the top of \$C_\text{jC}\$ will continue to be about \$12\:\text{V}\$ above that rapidly rising base voltage. Unfortunately, \$C_\text{jC}\$ can't adjust its voltage (discharging itself) as quickly, because of the value of \$R_2\$ which is 10 times more than \$R_1\$. Although the value of \$C_\text{jC}\$ may be half the value of \$C_\text{jE}\$, the sum of \$R_1\$ and \$R_2\$ is still more than 10 times larger than what's charging up \$C_\text{jE}\$. So \$C_\text{jC}\$ discharges more slowly, holding it's initial \$12\:\text{V}\$ potential longer, because it can only discharge via \$R_1+R_2+r_\text{b'}+r_\text{c'}\$ (which in this case is about 11 times more resistance.)

So, while the \$V_\text{CC}\$-connected end of \$R_2\$ is stuck at \$12\:\text{V}\$, the collector-connected end of \$R_2\$ can, in fact, rise up above \$V_\text{CC}\$ for a moment while \$C_\text{jC}\$ now discharges itself through \$R_1+R_2+r_\text{b'}+r_\text{c'}\$.

That's about it.

If you want to look over an RTL design then see: RTL NOR-gate quantitative design process.

  • \$\begingroup\$ Thank you both for the answers. And if there is a load resistance between the collector and gnd? \$\endgroup\$ – Kinka-Byo Mar 12 at 3:37
  • \$\begingroup\$ @Kinka-Byo Then this means you have a new Thevenin equivalent voltage and resistance at the collector. This means that \$C_\text{jC}\$ charges up to this new Thevenin voltage, instead, prior to yanking upward at \$t=10\:\text{ms}\$. This also means that there is a lower discharging resistance (so the discharge will happen somewhat faster.) \$\endgroup\$ – jonk Mar 12 at 17:30
  • \$\begingroup\$ @Kinka-Byo See my last note in the answer about designing RTL. \$\endgroup\$ – jonk Mar 13 at 4:09

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