I certainly cannot answer your question for sure. It makes no much sense to disable units smaller than 1 core, since it becomes a very fine-grained "feature set" that can be enabled or not, and the Cartesian product of all possible features would make myriad of possible CPU models. There are a lot of CPU models already, making them 10-100 times more will definitely not help!
Another aspect is that the billions of transistors are used (for the most part) in making caches, and for defective transistors there manufacturers definitely sell CPUs with parts of their on-die cache disabled (e.g. see, AMD Thorton vs AMD Barton).
But I can tell you an anecdote which I've heard from a person I trust. A long time ago I was a curious overclocker. In my days, the budget overclockable CPU of choice was the AMD Athlon Thoroughbred:
When mounting custom cooling solutions, one had to be very careful while attaching the heatsink, as it presses directly against the die. If you applied uneven pressure, the dies were notorious for cracking easily at the corners, if you applied force at one corner first.
This person had done exactly the same thing, a significant portion of one corner was gone, but the CPU was miraculously working fine, albeit at much reduced memory performance. The corner contained L2 cache only, so with that part gone, the caching protocol was somehow working around the now very defective die. It was probably reporting cache misses for all queries in that part, so the CPU was reduced to its L1 cache only (or only part of L2), so it was much slower in most tests, yet had virtually the same performance on tight loops.
In the same line of thought, it could be made that if an ALU is defective and is capable of somehow signalling back that it rejected work, the CPU may be capable of falling back on other ALUs. Whether this is being done by CPU manufacturers is unknown (and I doubt it), but the cache example (from 15 years ago) shows that it is definitely doable.