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I am designing a boost LED driver using LT3761

Using the datasheet examples I designed and ordered PCBs, assembled them, but every time I connect the power one of four things explode: fuse, driver, boost MOSFET or sense shunt. I tried many different LEDs, calculated and populated different sets of components, but the result is the same. I tried the exact values from the datasheet's first example, boost driver for 1A led, the result is the same.

I do not know what is wrong here.

For explode part of the question, I understand, that I give the energy from my battery which is sufficient for explosion and if I would use current limited power supply it would behave differently. But, the IC has all possible protections. How it goes into drawing so much energy for explosion...

I am designing the driver to be used from 20V to 50V. Tried 24V and 48V, both do same damage. Tried to power with a 24V battery and 48V power supply. Wires from source to the load are 20cm.

When I limit the power using a series resistor it does not blow. I do not have current limiting power supply.

Please see the attached schematic and the PCB.

It is in boost mode. The Inductor is 10uH.

I tried MOSFETS FDMS86201, NVMFS6B14NLT1G, FDMT800150DC

All parts sourced from Arrow.com

Thank you.

Schematic

PCB

This is top layer from official evaluation board design. Usual design with small gaps and copper regions. DC1772A EVL board top layer

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  • \$\begingroup\$ Comments are not for extended discussion; this conversation has been moved to chat. Any conclusions reached should be edited back into the question and/or any answer(s). \$\endgroup\$ – Dave Tweed Mar 13 at 14:03
  • \$\begingroup\$ We discourage broad, open-ended design review questions here on EE.SE, because the answer(s) tend to become long strings of unrelated edits and/or comments. While this might help you with your immediate problems, it is of no value to the site overall. We DO allow design review questions in which you explain your choices and then focus on a few points about which you still have doubts. To get a better feel of what is or is not acceptable, search for "design review" on the meta site. \$\endgroup\$ – Dave Tweed Mar 13 at 14:04
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That must be very frustrating.

I don't see any test results especially those that should be non-destructive attempts to characterize sections of the design.

Can you test the Boost FET path alone by injecting external voltage pulse at equiv Rs? The path in red is the current path of destruction. (pun intended)

I believe when Rs fuses open, then the IC fails 2nd with OV then avalanche failure. The avalanche diode may not be fast enough for recovery time. (?) Then the FET overheats. So FET specs and all other related datasheets are important to include in question..

The Gate pulse and current pulse sense ought to reveal your problem from resistance and Q charge effects. High quality measurement methods need to be done with calibrated spring probes. ( meaning flat mV traces on ground signal with current pulses flowing under it.)

enter image description here

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  • \$\begingroup\$ Added a picture of official evaluation board design. Their gaps look close. \$\endgroup\$ – Roman Simonyan Mar 12 at 7:32
  • \$\begingroup\$ OK but I cannot verify the paths for parasitic coupling is same from a quick layout glance. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Mar 12 at 15:53
  • \$\begingroup\$ If I could understand everything you say and do all the measurements you suggest I would not have the problem in the first place :) \$\endgroup\$ – Roman Simonyan Mar 12 at 16:04
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    \$\begingroup\$ It just verifies each part is doing its job testing in sections. Next time include DFT test points for new design. and a Polyfuse that heats up faster than the FET... OV = overvoltage \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Mar 12 at 16:05
  • \$\begingroup\$ buy (TEK) or make this from spring wire for your 10:1 calibrated probe and include same distance pads in future layouts for Design for Testability (DFT) i.stack.imgur.com/PSo3N.jpg if no spring just use resistor wire for now and tape. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Mar 12 at 16:08
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I am not sure if this is the issue, but it is the first thing that jumped at me when I saw your schematic.

You are using large ceramic capacitors in conjunction with paralleled Tantalum or Electrolythics for your bulk supply capacitance, although at first glance this might seem like a good idea, the input characteristics of a switching power supply are very likely to create unstable conditions at their inputs if some precautions are not taken.

The reason can be gleaned from this answer and the exact reason for your specific problem is very probably the exact same one that is shown here.

There is such thing as too little ESR to adequately compensate for the negative impedance presented by a switching power supply. When using ceramics or too low of an ESR for this type of application, you are likely to introduce an undamped resonances that can multiply the input voltage until it reaches destructive levels.

You have to pay attention to the ESR and provide enough dissipation elements (e.g., intentional series resistance) to dampen any oscillation that can be elicited by the circuitry. The combination of your inductor, wiring, and capacitance create a resonant tank that can be excited by the switcher and interacts with its negative impedance. If there is not enough resistance to dampen this oscillation an unstable condition arises which can multiply the input voltage by a large factor.

In your case assuming 50W load with an input of 50V your switcher could present a negative input impedance of -50Ω!!! At 25V it would be -12.5Ω!!! (this of course is a linearized over-simplification, but it illustrates the magnitude of the problem). If I only consider your ceramics, I get a resonant frequency of just 10kHz if I add your electrolytics it goes down to just 1kHz, either of those is below the operating frequency of your switcher which suggests that the linearized approximation would apply!!!

The cause of the negative impedance, your switcher feedback loop, will try to compensate for the oscillating input voltage which will interact non-linearly with the oscillations, very likely making it worse.

You should reconsider the amount of bulk decoupling you are using and test by looking at the input voltage (the lowest you can apply) with enough series resistance in your supply to avoid the whole system from blowing up. If you see large sustained oscillations at the input you would have found the problem.

This can be solved/improved by:

  • Adding some series resistance to your bulk capacitance. In most cases less than 1Ω should suffice, but given the large values of negative resistance that might be present, you should analyze the circuit in more detail to be sure.
  • Reducing the ceramic capacitors to place the resonance well above the switching frequency, so that it does not interact with your switcher.
  • Reducing the overall bulk capacitance, so as the resonance does not interact negatively with your switcher.
  • Increasing the wire gauge of the supply, reducing their length, and twisting them to reduce their parasitic inductance.
  • Changing the switching frequency. Given the chaotic aspects of the feedback it is likely you would be able to find a stable region of parameter space.
  • Modifying the switcher feedback loop, for the same reasons as above.
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