I just started reading about bandgap reference circuits (PTAT, CTAT generation, etc.) in CMOS and I see a lot of papers about something called trimming in relation to these.

What does it actually mean and why is it used?

  • \$\begingroup\$ Basically, individually adjusting each part. Don't have the time to explain in any more detail but someone else should be able to give a good answer. \$\endgroup\$
    – Hearth
    Mar 14, 2019 at 19:44

3 Answers 3


The output of the bandgap reference will vary from chip to chip because of processing differences. The primary effect in bipolar bandgap references is the variation of resistors in the circuit. Absolute value of these resistors is controlled to 20% or even 50% by process parameters. This problem can get more acute when different types of semiconductor resistor are used for curvature compensation.

Due to process variation, bandgap circuit is not operating with the designed current and/or current ratio in the 2 diodes. It will produce a different voltage and curvature over temperature. Trimming adjusts the resistors and hence the current back to design intent. The reference gets back to the desired voltage output and temperature performance.

The ICs I designed were in large, 1.2 um line or greater, processes. The references were trimmed using dedicated pads (octagonal to distinguish from wire bond pads) to blow metal fuses during wafer test. Other trimming, such as memory driving transistors is a solution for finer line processes and pad limited designs. I worked on one design that used poly fuse memory that the IC blew during production test. Much cheaper than adding the extra steps for EEPROM, Flash, etc.

The test engineers could predict what fuses to blow on a BG reference with one measurment. Often the LSB fuse was not blown until measuring the results of the higher fuse blow.

My understanding, which is 10 years out of date, is that laser trimming is expensive and only used when absolutely necessary. Laser trimmed structures must be relatively large, need fiducials, and cannot have anything else near them, above them or below them. Unless the laser is ablating fuses, the effect of a laser trim is not very predictable. Trimming is done closed loop and hence slowly. In addition to the time cost, Laser trimming machines are not cheap.

  • \$\begingroup\$ Ah. That makes a lot of sense now. So essentially, since bandgaps rely on PTAT and CTAT being in perfect sync., the resistors in those PTAT/CTAT circuits are of huge importance and trimming lets you get rid of the process variation after fabrication (by adjusting values of these resistors)? \$\endgroup\$ Mar 15, 2019 at 19:25
  • \$\begingroup\$ Yes, the PTAT and CTAT need to be balanced to try to get a temperature invariant voltage. Trimming compensates for process variation. I believe the primary variation to compensate is the resistors themselves. I am no BG expert. I copied references that were already designed for and working in other products first. \$\endgroup\$
    – jherbold
    Mar 16, 2019 at 6:29
  • \$\begingroup\$ Neither PTAT or CTAT are strictly linear with temperature so there is curvature. Resistors with different tempcos (say p+ doped Si) are used try to compensate these 2nd order shifts. The resistor value changes with temperature causing the PTAT and CTAT balance to change with temperature. This should create a more temperature stable output. \$\endgroup\$
    – jherbold
    Mar 16, 2019 at 6:31

The principle of the bandgap voltage reference is to balance the negative temperature coefficient (NTC) of a pn junction with the positive temperature coefficient(PTC) of the thermal voltage, Vt = kT/q.

3 main categories of variables: PVT (process, voltage and temperature)

For some reason, someone decided to call them PTAT/CTAT wasn't aware that PTC/NTC was already common long before bandgaps.

  • "PTAT"= PTC proportional to absolute temperature ( i.e. +ve tempco or PTC)
  • "CTAT"= NTC complementary to absolute temperature ( i.e. -ve tempco or NTC, like diodes)

Transistor and resistor, mismatch and tolerance, errors can be “trimmed out” by tuning a PTAT trimming resistor.

  • However, the resistor temperature coefficient (TC) is small, yet cannot be trimmed from 2nd order effects so they must be low TC materials.

  • most ceramic caps are PTAT or NTC, some are PTC and in between is NP0/C0G or 0+/-25ppm

  • Current-mirror mismatch is the deviation of required W/L ratio of the mirroring MOS transistors or areas of BJT transistors.

  • transistors have mismatch from variations in "ideality constant" and Early effect voltage"

    Process control tolerances before tuning:
    BJTs: β: ±30%
    MOS: µ: ±10%, Vth: ±100mV
    Resistors: R: ±20%
    Capacitors: C: ±5%
    Inductors: L: ±1%


It means (as @Hearth said) that each part gets individually adjusted. I'm not sure how it's done these days, but the last time I was paying attention it was done by carefully zapping the part with lasers. I can think of three different ways (including lasers) that it may be done these days (the other two are PROM-style fuses, and EEPROM-style floating-gate FETs).

It needs to be done because nothing analog is exactly precise. Everything depends on everything else, and so there's natural manufacturing variation that has to be taken into account.

  • \$\begingroup\$ For sensitive analog bits, the laser method is the most common as far as I know. Your other suggestions would introduce parasitics that laser trimming doesn't (or at least doesn't as badly) \$\endgroup\$
    – Hearth
    Mar 14, 2019 at 21:43
  • \$\begingroup\$ I know laser trimming was The Way 10 or 20 years ago, but I could see a budget precision (?) house wanting something cheaper. \$\endgroup\$
    – TimWescott
    Mar 14, 2019 at 22:54
  • \$\begingroup\$ It's still The Way today as far as I can tell. I still see datasheets on new devices stating that they're laser-trimmed for accuracy, and I've never heard of any other type of trimming short of actual trimpots. \$\endgroup\$
    – Hearth
    Mar 14, 2019 at 23:28
  • \$\begingroup\$ If the semiconductor process includes high voltage (20 volt) tunneling-electron-gate Electrically-Erasable ReadOnlyMemory, then other options exist. \$\endgroup\$ Mar 15, 2019 at 3:00

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