# If I need to find an MOSFET spice model with a particular length and width, where do I start?

I was using a 180nm NMOS and PMOS but now need to use an NMOS with about L=.36u and W=100u. I have two models but I dont think I can just change the length and width to any value.

How can I check if I can scale my current model to that size with a parameter, or what parameters do I check to make sure I can do that? I dont really see a "Wmin" or anything like that in my model, but I am sure there could be different names for them

Where do I go about finding a mosfet model knowing those two parameters I want to fulfill?

I am trying to use this NMOS in a diode connected configuration, and I was told that that size I am looking for would help get it deep into weak inversion

Right now I am using a TSMC .18u NMOS

.MODEL CMOSN NMOS ( LEVEL = 49
+VERSION = 3.1 ....

• You need to be much more specific. There are several dozens of spice model types (aka “levels”) and each one of those provides some support for multiple ranges and types of variation. If all the transistors are in the same technology, the more elaborate models are designed to properly scale with transistor size. Commented Mar 15, 2019 at 3:54
• @EdgarBrown I added the level 49 nmos I am using right now. Commented Mar 15, 2019 at 4:05
• MU * Cox is the K (the amps/volt^2). You have the Tox, so the Cox is just math. At 100/36, you have many picoFarads of gate-channel capacitance. Assume 50 uA/volt^2 at the K for a sub-0.25 micron Nchannel. At 1uA, you will be approx 1/15 volts above threshold (Ve = 0.06). Is this adequately low, to be in subtheshold. At 10 nanoAmps, you will be approx 6 milliVolts above threshold. Using W/L = 3. Commented Mar 15, 2019 at 11:33
• I'm pretty sure it violates the terms of the TSMC license to post their models online Commented Mar 15, 2019 at 12:58
• I found this model online on a forum. I believe it could have been a sample model. To be safe, I can remove it @Justin Commented Mar 15, 2019 at 14:00

It is unusual to seek a MOSFET model for particular values of W and L, except perhaps at the minimum allowed values of those parameters. Specifying the W and L that you want and using the vendor-supplied model is the usual route.

You need to contact TSMC, or whoever supplied the model parameters, to find out the applicable range of W and L for those parameters. If the parameters were extracted with the intent that they represent transistors larger than the minimum size, then you can use them as you described.

• How does someone usually contact them with that specific question for a spice model? Is there a regular method of contact for this sort of question? Commented Mar 15, 2019 at 14:31
• How did you obtain the model? Usually the organization that supplies the model will be able to tell you how the parameters where obtained. TSMC's own models are often covered under a non-disclosure agreement, so if you got the models directly from TSMC then you contact whoever you work with at TSMC. If you got the model parameters from MOSIS, then contact MOSIS. If you don't know the source of your model parameters then you shouldn't put much faith in your simulation results. Commented Mar 15, 2019 at 14:44
• I obtained it from this link (edaboard.com/…) It is a "sample MOS model for the TSMC 0.18 micron process" Commented Mar 15, 2019 at 15:47

Level 49 is a BSIM3 model. This family of models were developed precisely to account for all of the effects found when scaling down transistors in all of their regions of operation.

These are not merely theoretical first-principle models but instead rather elaborate curve fits that rely on parameter extractions from different-sized transistors in actual devices.

Their range of validity depends on the sizes of transistors used for the parameter extraction, but the usefulness of these models is precisely to be able to model minimum size transistors, as larger-feature transistors are simpler to model.

The parameter extraction tools tend to generate rather standardized reports that tell you exactly what transistor sizes (minimum/short/wide/large) were used to generate the model. See this example from a MOSIS extraction of a specific academic run of an TSMC 0.18µm process. Vendor models tend to be more general than this and would be divided instead into slow/avg/fast wafer run corners.

I have used such models over many orders of magnitude of W/L in all transistor operating regimes with extremely good agreement with reality. I’ve only encountered slight discrepancies in sub-threshold noise figures, were the models tend to overestimate them and does not account for shot noise.

• Just to clarify, the example you linked is not from TSMC, it is from MOSIS. The model parameters are for one particular production lot that MOSIS measured. These models may or may not represent "typical" values for the process. Those models are fine for academic purposes but not for high-volume commercial products. Commented Mar 15, 2019 at 14:49
• @ElliotAlderson It is a MOSIS parameter file for a very specific run of a TSMC 0.35 process. These are extracted for specific IC runs so that MOSIS users can verify the performance of the actual circuits in the actual ICs received. Vendors generally create more generic models than this with fast/avg/slow corner models, but the tools and methods used are essentially the same. Edited to clarify. Commented Mar 15, 2019 at 14:55
• What exactly is a "TSMC 0.35 process" vs a "TSMC 0.35 MOS model" ? Commented Mar 15, 2019 at 15:55
• @userP520 A "TSMC 0.18 MOS model" is a MOS model that is used to represent (in some form) an actual TSMC 0.18 process-manufactured IC. The models I linked to are for a very specific wafer lot or "run" of a multi-project wafer (MOSIS identifier T18H) of a very specific 0.18µm process (SCN018). Commercial vendor models will represent all of the guaranteed range of variability within all runs, this is done by providing at least three set of models for fast/avg/slow corners of the process. These parameters are guaranteed via measurements and adjustments done during the fabrication of the wafer. Commented Mar 15, 2019 at 16:07
• @userP520 to be even more specific, this MOSIS run was taped-out on 27 August 2001 and the wafers were received by MOSIS from TSMC on 27 September 2001. (mosis.com/db/pubf/WEBREPORTS?REQUEST=RunReport&RUNID=T18H) Commented Mar 15, 2019 at 16:14